# US 2016/0262255 A1 · Test board unit and apparatus for testing a semiconductor chip including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2016/0262255 A1 - Document ID: US20160262255A1 - Status: Published application - Kind: A1 - Application number: 14/846,053 - Filed: 2015-09-04 - Published: 2016-09-08 - Earliest claimed: 2015-03-04 - Assignees: SK hynix Inc.; Unitest Inc. - Applicants: SK hynix Inc.; Unitest Inc. - Inventors: Woo Sik JUNG; Byoung Seon KOH; Hyo Jin OH; Young Bae CHOI; Jin Young JUNG - Web page: https://patentgrep.com/patent/US20160262255A1 ## CPC - G01R 31/2863: {Contacting devices, e.g. sockets, burn-in boards or mounting fixtures (in general G01R1/04)} - G01R 1/0408: {Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets (G01R1/067 takes precedence; mass production testing systems G01R31/59; testing of connections G01R31/66; for testing printed circuit boards G01R31/2808)} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A test board unit may include a test board, a thermal tank and a heat-dissipating plate. The test board may be configured to provide a semiconductor chip with a test current. The thermal tank may be configured to dissipate heat generated in the semiconductor chip. The heat-dissipating plate may be coupled between the test board and the thermal tank and may be configured to transfer the heat from the semiconductor chip to the thermal tank. ## Claims ### Claim 1 A test board unit comprising: a test board configured to provide a semiconductor chip with a test current; a thermal tank configured to dissipate heat generated from the semiconductor chip; and a heat-dissipating plate interposed between the test board and the thermal tank and configured to transfer the heat to the thermal tank. ### Claim 2 (depends on 1) The test board unit of claim 1, wherein the thermal tank is in direct contact with the heat-dissipating plate. ### Claim 3 (depends on 1) The test board unit of claim 1, further comprising an insulating layer formed on an outer surface of the thermal tank. ### Claim 4 (depends on 1) The test board unit of claim 1, wherein the thermal tank has at least one heat-dissipating hole. ### Claim 5 (depends on 1) The test board unit of claim 1, further comprising a heat-dissipating via arranged in the test board to electrically connect the semiconductor chip with the heat-dissipating plate. ### Claim 6 (depends on 5) The test board unit of claim 5, wherein the heat-dissipating via include a thermal via having a copper layer formed on an inner surface of the thermal via. ### Claim 7 (depends on 1) The test board unit of claim 1, wherein the test board comprises a test pattern configured to provide the semiconductor chip with the test current, and the heat-dissipating plate is electrically connected to the test pattern. ### Claim 8 A test board unit comprising: a test board configured to provide a semiconductor chip with a test current; a thermal tank configured to dissipate heat generated from the semiconductor chip; and a heat-dissipating via arranged in the test board to electrically couple the semiconductor chip with the thermal tank. ### Claim 9 (depends on 8) The test board unit of claim 8, wherein the thermal tank is in contact with the test board. ### Claim 10 (depends on 9) The test board unit of claim 9, wherein substantially no gap exists between the thermal tank and the test board. ### Claim 11 (depends on 8) The test board unit of claim 8, further comprising an insulating layer formed on an outer surface of the thermal tank. ### Claim 12 (depends on 8) The test board unit of claim 8, wherein the thermal tank has at least one heat-dissipating hole. ### Claim 13 (depends on 8) The test board unit of claim 8, wherein the test board comprises a test pattern configured to provide the semiconductor chip with the test current, and the heat-dissipating plate is electrically connected to the test pattern. ### Claim 14 An apparatus for testing a semiconductor chip, the apparatus comprising: a test board configured to provide the semiconductor chip with a test current; a socket arranged on the test board and configured to accept the semiconductor chip; a thermal tank configured to dissipate heat generated from the semiconductor chip; and a heat-dissipating plate coupled between the test board and the thermal tank and configured to transfer the heat to the thermal tank. ### Claim 15 (depends on 14) The apparatus of claim 14, wherein the socket is arranged on a first surface of the test board, and the heat-dissipating plate is arranged on a second surface of the test board opposite to the first surface. ### Claim 16 (depends on 14) The apparatus of claim 14, wherein the socket comprises electrode terminals electrically connected to the semiconductor chip, and the heat-dissipating plate is configured to surround the electrode terminals of the socket. ### Claim 17 (depends on 14) The apparatus of claim 14, further comprising a heat-dissipating via arranged in the test board to electrically connect the semiconductor chip with the heat-dissipating plate. ### Claim 18 An apparatus for testing a semiconductor chip, the apparatus comprising: a test board configured to provide the semiconductor chip with a test current; a socket arranged on the test board and configured to accept the semiconductor chip; a thermal tank configured to dissipate heat generated from the semiconductor chip; and a heat-dissipating via arranged in the test board and configured to electrically couple the semiconductor chip with the thermal tank. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein the socket is arranged on a first surface of the test board, and the heat-dissipating plate is arranged on a second surface of the test board opposite to the first surface. ### Claim 20 (depends on 18) The apparatus of claim 18, wherein the thermal tank includes at least one heat-dissipating fin located on a lower surface of the thermal tank.