# US 2016/0261484 A9 · Chip multi processor and router for chip multi processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2016/0261484 A9 - Document ID: US20160261484A9 - Status: Published application - Kind: A9 - Application number: 13/680,014 - Filed: 2012-11-17 - Published: 2016-09-08 - Earliest claimed: 2011-12-12 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Woong Seo - Web page: https://patentgrep.com/patent/US20160261484A9 ## CPC - H04L 45/306: {Route determination based on the nature of the carried application} - H04L 45/00: Routing or path finding of packets in data switching networks (routing or path finding in wireless networks H04W40/00) - H04L 49/109: Integrated on microchip, e.g. switch-on-chip - H04L 49/1576: {Crossbar or matrix} - H04L 12/66: Arrangements for connecting between networks having differing types of switching systems, e.g. gateways - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Provided is a chip multi processor that supports both a packet switching method and a circuit switching method, and a router for the chip multi processor. According to an aspect, the chip multi processor includes a plurality of nodes that each include a router, and a plurality of links formed between the routers. Each of the routers may transfer a first type of data based on packet switching and a second type of data based on circuit switching. ## Claims ### Claim 1 A chip multi processor comprising: a plurality of nodes each comprising at least one of a processor and a memory; a plurality of routers respectively connected to the plurality of nodes; and a plurality of links formed between the routers, wherein each router transfers a first type of data based on packet switching and a second type of data based on circuit switching. ### Claim 2 (depends on 1) The chip multi processor of claim 1, wherein each node differentiates a value written in a specific area of data based on a request from an application or based on a characteristic of the application, to create the first type of data or the second type of data. ### Claim 3 (depends on 1) The chip multi processor of claim 1, wherein, in response to transferring the is second type of data, the plurality of routers establish a path between a source node that has generated the second type of data and a destination node that receives the second type of data, as a dedicated path for the second type of data. ### Claim 4 (depends on 1) The chip multi processor of claim 1, wherein each router comprises: a first buffer configured to store the first type of data; a second buffer configured to store the second type of data; an output port determining unit configured to determine an output port through which the first type of data or the second type of data is to be output; a switch unit configured to transfer the first type of data or the second type of data stored in the first buffer or the second buffer to the determined output port; and a switch controller configured to establish a link connected to the determined output port as a dedicated link for the second type of data. ### Claim 5 (depends on 4) The chip multi processor of claim 4, wherein each router further comprises a receiver configured to determine whether received data is the first type of data or the second type of data, to transfer the first type of data to the first buffer, and to transfer the second type of data to the second buffer. ### Claim 6 (depends on 4) The chip multi processor of claim 4, wherein the output unit comprises a crossbar switch. ### Claim 7 (depends on 4) The chip multi processor of claim 4, wherein, in response to the determined is output port being connected to a destination node for the second type of data, the controller generates a predetermined dedicated path setup success message. ### Claim 8 (depends on 4) The chip multi processor of claim 4, wherein, in response to the link connected to the determined output port already being allocated to another second type of data, the controller generates a predetermined dedicated path setup failure message or a standby message. ### Claim 9 A router for a chip multi processor, the router comprising: a first buffer configured to store a first type of data; a second buffer configured to store a second type of data; an output port determining unit configured to determine an output port through which the first type of data or the second type of data is to be output; an output unit configured to output the first type of data or the second type of data to the determined output port; and a controller configured to establish a dedicated link connected to the determined output port for the second type of data. ### Claim 10 (depends on 9) The router of claim 9, further comprising: a receiver configured to determine whether the received data is the first type of data or the second type of data, to transfer the first type of data to the first buffer, and to transfer the second type of data to the second buffer. ### Claim 11 (depends on 9) The router of claim 9, wherein the output unit includes a crossbar switch. ### Claim 12 (depends on 9) The router of claim 9, wherein, in response to the determined output port being connected to a destination node of the second type of data, the controller generates a predetermined dedicated path setup success message. ### Claim 13 (depends on 9) The router of claim 9, wherein, in response to a link connected to the determined output port already being allocated to another second type of data, the controller generates a predetermined dedicated path setup failure message or a standby message. ### Claim 14 (depends on 9) The router of claim 9, wherein the first type of data corresponds to a message that is transferred based on packet switching, and the message includes a plurality of packets each having header information and which are capable of being transferred independently. ### Claim 15 (depends on 9) The router of claim 9, wherein the second type of data corresponds to a message that is transferred based on circuit switching, and the message has single packet with header information. ### Claim 16 A chip multiprocessor, comprising: a plurality of processing nodes configured to process data; a plurality of routers configured to route data between the plurality of processing nodes during processing, wherein the plurality of routers selectively configure as a packet switching network and as a circuit switching network, based on the type of data to be routed. ### Claim 17 (depends on 16) The chip multiprocessor of claim 16, wherein, in response to a first type of data being processed, the plurality of routers configure as the packet switching network in which a path between a source router and a destination router is shared during transmission of the first type of data between the source router and the destination router. ### Claim 18 (depends on 16) The chip multiprocessor of claim 16, wherein, in response to a second type of data being processed, the plurality of routers configure as the circuit switching network in which a path between a source router and a destination router is not shared during transmission of the second type of data between the source router and the destination router. ### Claim 19 (depends on 18) The chip multiprocessor of claim 18, wherein the second type of data corresponds to an application that requests real-time processing.