# US 2016/0260802 A1 · Nanowire transistor devices and forming techniques

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- Number: US 2016/0260802 A1
- Document ID: US20160260802A1
- Status: Published application
- Kind: A1
- Application number: 15/155,806
- Filed: 2016-05-16
- Published: 2016-09-08
- Earliest claimed: 2011-12-23
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: GLENN A. GLASS; KELIN J. KUHN; SEIYON KIM; ANAND S. MURTHY; DANIEL B. AUBERTINE
- Web page: https://patentgrep.com/patent/US20160260802A1

## CPC

- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/853: {comprising FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

## Claims

### Claim 1

An integrated circuit, comprising:
a multilayer stack of a first type, the multilayer stack of the first type comprising first and second material layers, wherein the second material layer comprises a channel nanowire; and
a multilayer stack of a second type, the multilayer stack of the second type comprising first and second material layers, wherein the second material layer comprises a channel nanowire;
wherein at least one horizontal plane passes through the respective first material layers of the multilayer stack of the first type and the multilayer stack of the second type, and the respective first material layers through which the horizontal plane passes are configured with at least one of different thicknesses and different semiconductor materials.

### Claim 2 (depends on 1)

The integrated circuit of claim 1 further comprising a plurality of fins, wherein each fin extends from a substrate and includes a multilayer stack of the first type or a multilayer stack of the second type thereon.

### Claim 3 (depends on 2)

The integrated circuit of claim 2 wherein fins having a multilayer stack of the first type thereon are configured differently than fins having a multilayer stack of the second type thereon.

### Claim 4 (depends on 1)

The integrated circuit of claim 1 wherein each respective channel nanowire comprises at least one of germanium, silicon, silicon germanium, a III-V element, or a III-V compound.

### Claim 5 (depends on 1)

The integrated circuit of claim 1 wherein the channel nanowire of the first type multilayer stack comprises germanium or silicon, or an alloy thereof, and the channel nanowire of the second type multilayer stack comprises one or more III-V materials.

### Claim 6 (depends on 1)

The integrated circuit of claim 1 wherein the respective channel nanowires of both the first and second type multilayer stacks are configured with different polarities.

### Claim 7 (depends on 1)

The integrated circuit of claim 1 further comprising:
a pair of source and drain regions adjacent the channel nanowire of the first type multilayer stack;
a pair of source and drain regions adjacent the channel nanowire of the second type multilayer stack;
an all-around gate between each source drain pair; and
a contact on each source and drain region.

### Claim 8

A nanowire transistor device, comprising:
a first multilayer stack comprising a first channel area having a first nanowire; and
a second multilayer stack comprising a second channel area having a second nanowire;
wherein the first nanowire shares a common horizontal plane with the second nanowire, and the first nanowire is configured with at least one of different thicknesses and different semiconductor materials than the second nanowire.

### Claim 9 (depends on 8)

The device of claim 8 wherein at least one of the first and second nanowires comprises germanium, silicon, or silicon germanium.

### Claim 10 (depends on 8)

The device of claim 8 wherein at least one of the first and second nanowires comprises a III-V compound.

### Claim 11 (depends on 8)

The device of claim 8 wherein the first nanowire comprises germanium, silicon, or silicon germanium, and the second nanowire comprises one or more III-V materials.

### Claim 12 (depends on 8)

The device of claim 8 further comprising:
a pair of source and drain regions adjacent the channel area having a first nanowire;
a pair of source and drain regions adjacent the channel area having a second nanowire;
an all-around gate between the source drain pair adjacent the channel area having a first nanowire;
an all-around gate between the source drain pair adjacent the channel area having a second nanowire; and
a contact on each source and drain region.

### Claim 13 (depends on 8)

The device of claim 8 wherein the first multilayer stack is configured for one of PMOS or NMOS and the second multilayer stack is configured for the other of PMOS or NMOS.

### Claim 14

A nanowire transistor device, comprising:
a multilayer stack comprising a channel area having a nanowire; and
a fin comprising a channel area;
wherein the nanowire of the multilayer stack is configured differently than the fin.

### Claim 15 (depends on 14)

The device of claim 14 wherein the nanowire comprises germanium, silicon, or silicon germanium.

### Claim 16 (depends on 14)

The device of claim 14 wherein the nanowire comprises a III-V compound.

### Claim 17 (depends on 14)

The device of claim 14 wherein the nanowire comprises germanium, silicon, or silicon germanium, and the fin comprises one or more III-V materials.

### Claim 18 (depends on 14)

The device of claim 14 wherein the nanowire comprises one or more III-V materials, and the fin comprises germanium, silicon, or silicon germanium.

### Claim 19 (depends on 14)

The device of claim 14 further comprising:
a pair of source and drain regions adjacent the channel area having a nanowire;
a pair of source and drain regions adjacent the channel area of the fin;
an all-around gate between the source drain pair adjacent the channel area having a nanowire;
an multi-gate between the source drain pair adjacent the channel area of the fin; and
a contact on each source and drain region.

### Claim 20 (depends on 14)

The device of claim 14 wherein the multilayer stack is configured for one of PMOS or NMOS and the fin is configured for the other of PMOS or NMOS.