# US 2016/0260779 A1 · Non-volatile resistive random access memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2016/0260779 A1 - Document ID: US20160260779A1 - Status: Published application - Kind: A1 - Application number: 14/750,192 - Filed: 2015-06-25 - Published: 2016-09-08 - Earliest claimed: 2015-03-06 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kabushiki Kaisha Toshiba - Inventors: Tomohito KAWASHIMA; Shosuke FUJII - Web page: https://patentgrep.com/patent/US20160260779A1 ## CPC - H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays} - G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites} - G11C 13/0064: {Verifying circuits or methods} - G11C 13/0069: {Writing or programming circuits or methods} - H10N 70/245: {the species being metal cations, e.g. programmable metallization cells} - H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices} - H10N 70/8416: {adapted for supplying ionic species} - H10N 70/883: {Oxides or nitrides} - H10N 70/8833: {Binary metal oxides, e.g. TaOx} - G11C 2013/0092: {Write characterized by the shape, e.g. form, length, amplitude of the write pulse} - G11C 2213/32: Material having simple binary metal oxide structure - G11C 2213/33: Material including silicon - G11C 2213/34: Material includes an oxide or a nitride - G11C 2213/51: Structure including a barrier layer preventing or limiting migration, diffusion of ions or charges or formation of electrolytes near an electrode - G11C 2213/56: Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way - G11C 2213/71: Three dimensional array - G11C 2213/77: Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract According to one embodiment, a resistive random access memory device includes a first wiring extending in a first direction, a first ion source layer provided in a first portion on the first wiring and a first variable resistance layer provided on the first ion source layer. The resistive random access memory device also includes a second wiring, which is provided on the first variable resistance layer, faces the first portion, and extends in a second direction different from the first direction. The resistive random access memory device also includes a second variable resistance layer provided in a second portion on the second wiring, a second ion source layer provided on the second variable resistance layer and a third wiring, which is provided on the second ion source layer, faces the second portion, and extends in the first direction. ## Claims ### Claim 1 A resistive random access memory device, comprising: a first wiring extending in a first direction; a first ion source layer provided in a first portion on the first wiring; a first variable resistance layer provided on the first ion source layer; a second wiring, which is provided on the first variable resistance layer, faces the first portion, and extends in a second direction different from the first direction; a second variable resistance layer provided in a second portion on the second wiring; a second ion source layer provided on the second variable resistance layer; and a third wiring, which is provided on the second ion source layer, faces the second portion, and extends in the first direction, the first ion source layer being formed from a material different from that of the second ion source layer. ### Claim 2 (depends on 1) The device according to claim 1, wherein the first variable resistance layer is formed from a material different from that of the second variable resistance layer. ### Claim 3 (depends on 1) The device according to claim 1, wherein the second ion source layer contains silver, copper, gold, aluminum, iron, manganese, cobalt, nickel, or zinc, and the second variable resistance layer contains silicon oxide, silicon, aluminum oxide, hafnium oxide, niobium oxide, zirconium oxide, vanadium oxide, or molybdenum oxide. ### Claim 4 (depends on 1) The device according to claim 1, wherein the first variable resistance layer contains hafnium oxide, silicon, aluminum oxide, niobium oxide, zirconium oxide, vanadium oxide, or molybdenum oxide, and the first ion source layer contains titanium, tantalum, titanium nitride, tantalum nitride, tungsten nitride, zirconium nitride, or titanium tungsten. ### Claim 5 (depends on 1) The device according to claim 1, wherein the second variable resistance layer has a thickness different from that of the first variable resistance layer. ### Claim 6 (depends on 1) The device according to claim 1, wherein the first variable resistance layer has a thickness thinner than that of the second variable resistance layer. ### Claim 7 (depends on 1) The device according to claim 1, wherein the second variable resistance layer is disposed immediately above the first variable resistance layer. ### Claim 8 (depends on 1) The device according to claim 1, wherein a write-in pulse to be applied to the first variable resistance layer and a write-in pulse to be applied to the second variable resistance layer are different in shape. ### Claim 9 (depends on 1) The device according to claim 1, wherein an application time for a write-in pulse to be applied to the first variable resistance layer is different from an application time for a write-in pulse to be applied to the second variable resistance layer. ### Claim 10 (depends on 1) The device according to claim 1, wherein an application time for a write-in pulse to be applied to the first variable resistance layer is longer than an application time for a write-in pulse to be applied to the second variable resistance layer. ### Claim 11 (depends on 1) The device according to claim 1, wherein a verify pulse to be applied to the first variable resistance layer and a verify pulse to be applied to the second variable resistance layer are different in shape. ### Claim 12 (depends on 1) The device according to claim 1, wherein an application time for a verify pulse to be applied to the first variable resistance layer is different from an application time for a verify pulse to be applied to the second variable resistance layer. ### Claim 13 (depends on 1) The device according to claim 1, wherein an application time for a verify pulse to be applied to the first variable resistance layer is longer than an application time for a verify pulse to be applied to the second variable resistance layer. ### Claim 14 A resistive random access memory device, comprising: a first wiring extending in a first direction; a first ion source layer, which is provided in a first portion on the first wiring, and has a first ion source; a first variable resistance layer provided on the first ion source layer; a second wiring, which is provided on the first variable resistance layer, faces the first portion, and extends in a second direction different from the first direction; a second variable resistance layer provided in a second portion on the second wiring; a second ion source layer, which is provided on the second variable resistance layer, and has a second ion source and a second barrier metal; and a third wiring, which is provided on the second ion source layer, faces the second portion, and extends in the first direction, the second ion source layer having an upper surface which is rougher as compared with the first ion source layer. ### Claim 15 (depends on 14) The device according to claim 14, wherein the first variable resistance layer has a thickness different from that of the second variable resistance layer. ### Claim 16 (depends on 14) The device according to claim 14, wherein the first variable resistance layer has a thickness thinner than that of the second variable resistance layer. ### Claim 17 (depends on 14) The device according to claim 14, wherein the second variable resistance layer is disposed immediately above the first variable resistance layer. ### Claim 18 (depends on 14) The device according to claim 14, wherein an application time for a write-in pulse to be applied to the first variable resistance layer is longer than an application time for a write-in pulse to be applied to the second variable resistance layer. ### Claim 19 (depends on 14) The device according to claim 14, wherein an application time for a write-in pulse to be applied to the first variable resistance layer is longer than an application time for a write-in pulse to be applied to the second variable resistance layer, and the first variable resistance layer has a thickness thinner than that of the second variable resistance layer. ### Claim 20 (depends on 14) The device according to claim 14, wherein the second ion source aggregates more than the first ion source.