# US 2016/0260754 A1 · Array substrate and method for manufacturing the same, and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2016/0260754 A1 - Document ID: US20160260754A1 - Status: Published application - Kind: A1 - Application number: 14/443,474 - Filed: 2014-10-01 - Published: 2016-09-08 - Earliest claimed: 2014-05-29 - Assignees: Boe Technology Group Co., Ltd. - Applicants: Boe Technology Group Co., Ltd. - Inventors: Shuang SUN; Seungjin CHOI; Jing NIU; Fangzhen ZHANG - Web page: https://patentgrep.com/patent/US20160260754A1 ## CPC - G02F 1/13439: {characterised by their electrical, optical, physical properties; materials therefor; method of making} - G02F 1/133345: {Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence)} - G02F 1/134309: {characterised by their geometrical arrangement} - G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer} - G02F 1/136286: {Wiring, e.g. gate line, drain line} - G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} - H10D 30/6728: {Vertical TFTs} - H10D 30/6729: {characterised by the electrodes} - H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes} - H10D 30/6739: {Conductor-insulator-semiconductor electrodes} - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 84/01: Manufacture or treatment - H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates - H10D 86/01: Manufacture or treatment - H10D 86/021: {of multiple TFTs} - H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies} - H10D 86/0231: {using masks, e.g. half-tone masks} - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/60: wherein the TFTs are in active matrices - G02F 1/136231: {for reducing the number of lithographic steps} - G02F 1/136236: {using a grey or half tone lithographic process} - G02F 1/13625: {Patterning using multi-mask exposure} - G02F 1/136295: {Materials; Compositions; Manufacture processes} - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract An array substrate and manufacturing method thereof and a display device. The display device includes a pixel electrode, including a portion in a display region and a portion in a non-display region; a first electrode formed on the non-display region of the pixel electrode; a passivation layer formed on the pixel electrode and the first electrode, which includes a via hole located over the first electrode; an active layer and a second electrode that are formed on the passivation layer, the active layer being connected to the first electrode through the via hole of the passivation layer. With the array substrate and the manufacturing method thereof, the manufacturing cost is reduced, the corrosion to an electrode material is lessened, and quality of the array substrate is enhanced. ## Claims ### Claim 1 An array substrate, comprising a pixel electrode, including a portion in a display region and a portion in a non-display region; a first electrode formed on the non-display region of the pixel electrode; a passivation layer formed on the pixel electrode and the first electrode, which includes a via hole located over the first electrode; and an active layer and a second electrode that are formed on the passivation layer, the active layer being connected to the first electrode through the via hole of the passivation layer. ### Claim 2 (depends on 1) The array substrate according to claim 1, further comprising: a common electrode, which lies on the passivation layer, and is formed by a portion of the active layer in correspondence with the display region of the pixel electrode and subjected to a plasma treatment. ### Claim 3 (depends on 1) The array substrate according to claim 1, further comprising: an etch barrier layer formed on the active layer and the second electrode. ### Claim 4 (depends on 1) The array substrate according to claim 1, further comprising: a gate electrode and a gate line that are formed on a glass substrate; and a gate insulating layer formed on the gate electrode and the gate line, with the pixel electrode formed on the gate insulating layer. ### Claim 5 (depends on 1) The array substrate according to claim 1, wherein: the first electrode is a source electrode, the second electrode is a drain electrode; or, the first electrode is a drain electrode, and the second electrode is a source electrode. ### Claim 6 (depends on 4) The array substrate according to claim 4, wherein: a material for the gate electrode, the first electrode and/or the second electrode is copper or a copper alloy. ### Claim 7 (depends on 1) The array substrate according to claim 1, wherein: a position of the second electrode does not overlap with the first electrode. ### Claim 8 (depends on 1) A display device, comprising the array substrate according to claim 1. ### Claim 9 A manufacturing method of an array substrate, comprising: forming a pattern that includes a pixel electrode and a first electrode, the pixel electrode including a portion in a display region and a portion in a non-display region, the first electrode being located on the non-display region of the pixel electrode; forming a pattern of a passivation layer on the pixel electrode and the first electrode, the passivation layer including a via hole located over the first electrode; and forming a pattern that includes an active layer and a second electrode on the passivation layer, the active layer being connected to the first electrode through the via hole of the passivation layer. ### Claim 10 (depends on 9) The manufacturing method of the array substrate according to claim 9, further comprising: conducting a plasma treatment on a portion of the active layer in correspondence with the display region of the pixel electrode, so as to form a common electrode. ### Claim 11 (depends on 9) The manufacturing method of the array substrate according to claim 9, further comprising: forming a pattern of an etch barrier layer on the active layer and the second electrode. ### Claim 12 (depends on 9) The manufacturing method of the array substrate according to claim 9, further comprising: forming a pattern that includes a gate electrode and a gate line on a glass substrate, forming a pattern of a gate insulating layer on the gate electrode and the gate line, and forming a pixel electrode on the gate insulating layer. ### Claim 13 (depends on 9) The manufacturing method of the array substrate according to claim 9, wherein, forming a transparent conductive layer thin film and a first electrode layer thin film in sequence; coating a first photoresist on the first electrode layer thin film and subjecting it to exposure and development with a gray-tone mask, so as to form a first photoresist fully-retained region in correspondence with a first electrode zone to be formed, a first photoresist half-retained region in correspondence with a zone where the portion of the pixel electrode in the display region is to be formed, and a first photoresist fully-removed region in correspondence with other zone than those stated above; conducting a first etching, so as to etch off the first electrode layer thin film and the transparent conductive layer thin film at the first photoresist fully-removed region, performing an aching treatment on the first photoresist, so that the photoresist at the first photoresist fully-retained region is thinned, and the photoresist at the first photoresist half-retained region is fully removed, and then conducting a second etching, so as to etch off the first electrode layer thin film at the first photoresist half-retained region; and removing the photoresist, so as to form a pattern that includes the pixel electrode and the first electrode. ### Claim 14 (depends on 9) The manufacturing method of the array substrate according to claim 9, wherein, forming an active layer thin film and a second electrode layer thin film in sequence on the passivation layer; coating a second photoresist on the second electrode layer thin film and subjecting it to exposure and development with a gray-tone mask, so as to form a second photoresist fully-retained region in correspondence with a second electrode zone and a data line zone that are to be formed, a second photoresist half-retained region in correspondence with an active layer zone to be formed, and a second photoresist fully-removed region in correspondence with other zone than those stated above; conducting a first etching, so as to etch off the second electrode layer thin film and the active layer thin film at the second photoresist fully-removed region, performing an aching treatment on the second photoresist, so that the photoresist at the second photoresist fully-retained region is thinned, and the photoresist at the second photoresist half-retained region is fully removed, and then conducting a second etching, so as to etch off the second electrode layer thin film at the second photoresist half-retained region; and removing the photoresist, so as to form a pattern that includes the second electrode, the data line and the active layer. ### Claim 15 (depends on 12) The manufacturing method of the array substrate according to claim 12, wherein, a material for the gate electrode, the first electrode and/or the second electrode is copper or a copper alloy. ### Claim 16 (depends on 9) The manufacturing method of the array substrate according to claim 9, wherein, a position of the second electrode does not overlap with the first electrode. ### Claim 17 (depends on 9) The manufacturing method of the array substrate according to claim 9, wherein, the first electrode is a source electrode, the second electrode is a drain electrode; or, the first electrode is a drain electrode, and the second electrode is a source electrode. ### Claim 18 (depends on 8) The display device according to claim 8, further comprising: a common electrode, which lies on the passivation layer, and is formed by a portion of the active layer in correspondence with the display region of the pixel electrode and subjected to a plasma treatment. ### Claim 19 (depends on 8) The display device according to claim 8, further comprising: an etch barrier layer formed on the active layer and the second electrode. ### Claim 20 (depends on 8) The display device according to claim 8, further comprising: a gate electrode and a gate line that are formed on a glass substrate; and a gate insulating layer formed on the gate electrode and the gate line, with the pixel electrode formed on the gate insulating layer.