# US 2016/0260698 A1 · Semiconductor memory device

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- Number: US 2016/0260698 A1
- Document ID: US20160260698A1
- Status: Published application
- Kind: A1
- Application number: 14/819,222
- Filed: 2015-08-05
- Published: 2016-09-08
- Earliest claimed: 2015-03-06
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Sung Lae OH; Dae Sung EOM
- Web page: https://patentgrep.com/patent/US20160260698A1

## CPC

- H10B 43/40: characterised by the peripheral circuit region
- H10B 41/40: characterised by the peripheral circuit region
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor memory device to which a Peri Under Cell (PUC) structure is applied is disclosed. The semiconductor memory device includes a word line multilayered structure formed in a cell region, and extending from across the cell region; and a slimming region including a step-shaped pad structure in the word line multilayered structure.

## Claims

### Claim 1

A semiconductor memory device comprising:
a word line multilayered structure formed in a cell region, and extending across the cell region; and
a slimming region including a step-shaped pad structure in the word line multilayered structure.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1, wherein the word line multilayered structure includes alternately stacked conductive materials and insulation films.

### Claim 3 (depends on 1)

The semiconductor memory device according to claim 1, further comprising:
a first contact coupled to the step-shaped pad structure of the slimming region.

### Claim 4 (depends on 1)

The semiconductor memory device according to claim 1, further comprising:
a peripheral region below the cell region.

### Claim 5 (depends on 4)

The semiconductor memory device according to claim 4, further comprising:
an active region in the peripheral region;
a gate electrode perpendicular to the active region; and
a junction region in the active region at both sides of the gate electrode.

### Claim 6 (depends on 1)

The semiconductor memory device according to claim 1, further comprising:
a bit line contact plug passing through the word line multilayered structure; and
a plurality of bit lines coupled to the bit line contact plug, and perpendicular to the word line multilayered structure.

### Claim 7

A semiconductor memory device comprising:
a first word line multilayered structure in a cell region, and extending across the cell region;
a first slimming region in the first word line multilayered structure;
a second word line multilayered structure in the cell region, and extending across the cell region; and
a second slimming region formed in the second word line multilayered structure.

### Claim 8 (depends on 7)

The semiconductor memory device according to claim 7, wherein the word line multilayered structure includes alternately stacked conductive materials and insulation films.

### Claim 9 (depends on 7)

The semiconductor memory device according to claim 7, wherein each of the first and second sliming regions includes:
a step-shaped pad structure in the word line multilayered structure.

### Claim 10 (depends on 9)

The semiconductor memory device according to claim 9, wherein the step-shaped pad structure includes:
a first surface that decreases in height going toward where the word line multilayered structure extends; and
a second surface on that increases in height toward where the word line multilayered structure extends.

### Claim 11 (depends on 10)

The semiconductor memory device according to claim 10, wherein the first surface and the second surface of the step-shaped pad structure are symmetrical or asymmetrical to each other.

### Claim 12 (depends on 7)

The semiconductor memory device according to claim 7, wherein the first word line multilayered structure and the second word line multilayered structure are spaced apart from each other by a slit.

### Claim 13 (depends on 12)

The semiconductor memory device according to claim 12, further comprising:
a first contact formed in the step-shaped pad structure of the first slimming region and the second slimming region;
a second contact formed in the slit; and
a metal line coupled to the first contact and the second contact.

### Claim 14 (depends on 7)

The semiconductor memory device according to claim 7, further comprising:
a bit line contact plug formed to pass through the first word line multilayered structure and the second word line multilayered structure; and
a plurality of bit lines coupled to the bit line contact plug, and perpendicular to the first word line multilayered structure and the second word line multilayered structure.

### Claim 15 (depends on 7)

The semiconductor memory device according to claim 7, further comprising:
a peripheral region arranged below the cell region.

### Claim 16 (depends on 15)

The semiconductor memory device according to claim 15, further comprising:
an active region arranged in the peripheral region;
a gate electrode perpendicular to the active region; and
a junction region formed in the active region at both sides of the gate electrode.

### Claim 17 (depends on 16)

The semiconductor memory device according to claim 16, further comprising:
a metal line coupled to the junction region,
wherein the metal line is coupled to the second contact.

### Claim 18

A semiconductor memory device comprising:
a cell region in which a word line multilayered structure is formed;
a peripheral region arranged below the cell region; and
a slimming region arranged in the cell region, suitable for coupling the cell region to the peripheral region, and including a pad structure formed by etching the word line multilayered structure of the cell region.

### Claim 19 (depends on 18)

The semiconductor memory device according to claim 18, further comprising:
an active region arranged in the peripheral region;
a gate electrode perpendicular to the active region;
a junction region formed in the active region at both sides of the gate electrode;
a bit line contact plug formed to pass through the word line multilayered structure; and
a plurality of bit lines coupled to the bit line contact plug, and perpendicular to the word line multilayered structure.

### Claim 20 (depends on 18)

The semiconductor memory device according to claim 18, wherein the pad structure includes a step shape having a first surface that reduces in height in a direction in which the word line multilayered structure extends, and a second surface that increases in height in the direction in which the word line multilayered structure extends.