# US 2016/0260680 A1 · Method for manufacturing semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2016/0260680 A1 - Document ID: US20160260680A1 - Status: Published application - Kind: A1 - Application number: 15/058,282 - Filed: 2016-03-02 - Published: 2016-09-08 - Earliest claimed: 2015-03-05 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Kenji SAKATA; Tsuyoshi KIDA; Yoshihiro ONO - Web page: https://patentgrep.com/patent/US20160260680A1 ## CPC - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 70/611: {for connecting multiple chips together} - H10W 70/635: {Through-vias} - H10W 90/00: Package configurations - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon - H10W 72/01235: {by plating, e.g. electroless plating or electroplating} - H10W 72/01257: {by reflowing} - H10W 72/01323: {in liquid form, e.g. by dispensing droplets or by screen printing} - H10W 72/01336: {in solid form, e.g. by using a powder or by laminating a foil} - H10W 72/0198: {batch processes} - H10W 72/07141: {Means for applying energy, e.g. ovens or lasers} - H10W 72/07173: {Means for moving chips, wafers or other parts, e.g. conveyor belts} - H10W 72/07178: {Means for aligning} - H10W 72/072: {of bump connectors} - H10W 72/07211: {Treating the bond pad before connecting, e.g. by applying flux or cleaning} - H10W 72/07223: {Active alignment, e.g. using optical alignment using marks or sensors} - H10W 72/07232: {Compression bonding, e.g. thermocompression bonding} - H10W 72/07234: {Using a reflow oven} - H10W 72/07236: {Soldering or alloying} - H10W 72/07237: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy} - H10W 72/073: {of die-attach connectors} - H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy} - H10W 72/07338: {hardening the adhesive by curing, e.g. thermosetting} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/30: Die-attach connectors - H10W 72/354: {comprising polymers} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method for manufacturing a semiconductor device includes the steps of mounting a Si interposer over a printed wiring substrate, plasma-cleaning an upper surface of the Si interposer, disposing an NCF over the upper surface of the Si interposer, and mounting a semiconductor chip over the upper surface of the Si interposer through the NCF. Also, the method includes the step of electrically coupling each of plural electrodes of a second substrate and each of plural electrode pads of the semiconductor chip with each other through plural bump electrodes by reflow, and the surface of the Si interposer is plasma-cleaned before attaching the NCF to the Si interposer. ## Claims ### Claim 1 A method for manufacturing a semiconductor device, comprising the steps of: (a) plasma-cleaning an upper surface of a chip support substrate that includes the upper surface where a plurality of electrodes are formed and a lower surface on the opposite side of the upper surface; (b) after the step (a), disposing an insulative adhesive over the upper surface of the chip support substrate; (c) after the step (b), mounting a semiconductor chip on the upper surface of the chip support substrate through the insulative adhesive; and (d) after the step (c), heating the chip support substrate mounted with the semiconductor chip and the insulative adhesive by reflow, and electrically coupling each of the electrodes of the chip support substrate and each of a plurality of electrode pads of the semiconductor chip with each other through a plurality of bump electrodes, wherein, in the step (d), each of the electrodes and each of the electrode pads are electrically coupled with each other through the bump electrodes in a state the insulative adhesive is disposed around each of the bump electrodes. ### Claim 2 (depends on 1) The method for manufacturing a semiconductor device according to claim 1, further comprising the steps of: before the step (a), baking the chip support substrate; and between the step (b) and the step (c), baking the insulative adhesive, wherein, in the step of baking the insulative adhesive, the insulative adhesive is baked at a temperature lower than a bake temperature of the chip support substrate in the step of baking the chip support substrate. ### Claim 3 (depends on 1) The method for manufacturing a semiconductor device according to claim 1, further comprising the steps of: before the step (a), baking the chip support substrate; and between the step (b) and the step (c), baking the insulative adhesive, wherein, in the step of baking the insulative adhesive, the insulative adhesive is baked within a time shorter than a bake time of the chip support substrate in the step of baking the chip support substrate. ### Claim 4 (depends on 1) The method for manufacturing a semiconductor device according to claim 1, wherein, in the step (c), the semiconductor chip and the chip support substrate are positioned with each other recognizing marks formed outside the insulative adhesive of the upper surface of the chip support substrate. ### Claim 5 (depends on 1) The method for manufacturing a semiconductor device according to claim 1, wherein, in the step (c), after positioning the semiconductor chip and the chip support substrate with each other, each of solders coated at each distal end of the bump electrodes is heated and deformed at a temperature lower than the melting point of the solder, and each of the electrodes is dented into each of the solder. ### Claim 6 (depends on 5) The method for manufacturing a semiconductor device according to claim 5, wherein Au plating is formed over the surface of each of the electrodes of the chip support substrate, and the Au plating and the solder are coupled with each other. ### Claim 7 A method for manufacturing a semiconductor device, comprising the steps of: (a) mounting a second substrate over a first substrate with the second substrate including an upper surface where a plurality of electrodes are formed and a lower surface on the opposite side of the upper surface; (b) after the step (a), baking the first substrate; (c) after the step (b), plasma-cleaning the upper surface of the second substrate; (d) after the step (c), disposing an insulative adhesive over the upper surface of the second substrate; (e) after the step (d), mounting a semiconductor chip over the upper surface of the second substrate through the insulative adhesive; and (f) after the step (e), heating the second substrate mounted with the semiconductor chip and the insulative adhesive by reflow, and electrically coupling each of the electrodes of the second substrate and each of a plurality of electrode pads of the semiconductor chip with each other through a plurality of bump electrodes, wherein in the step (f), each of the electrodes and each of the electrode pads are electrically coupled with each other through the bump electrodes in a state the insulative adhesive is disposed around each of the bump electrodes. ### Claim 8 (depends on 7) The method for manufacturing a semiconductor device according to claim 7, further comprising the step of: between the step (d) and the step (e), baking the insulative adhesive, wherein, in the step of baking the insulative adhesive, the insulative adhesive is baked at a temperature lower than a bake temperature of the first substrate in the step (b). ### Claim 9 (depends on 7) The method for manufacturing a semiconductor device according to claim 7, further comprising the step of: between the step (d) and the step (e), baking the insulative adhesive, wherein, in the step of baking the insulative adhesive, the insulative adhesive is baked within a time shorter than a bake time of the first substrate in the step (b). ### Claim 10 (depends on 7) The method for manufacturing a semiconductor device according to claim 7, wherein, in the step (e), the semiconductor chip and the second substrate are positioned with each other recognizing marks formed outside the insulative adhesive of the upper surface of the second substrate. ### Claim 11 (depends on 7) The method for manufacturing a semiconductor device according to claim 7, wherein, in the step (e), after positioning the semiconductor chip and the second substrate with each other, each of solders coated at each distal end of the bump electrodes is heated and deformed at a temperature lower than the melting point of the solder, and each of the electrodes is dented into each of the solder. ### Claim 12 (depends on 11) The method for manufacturing a semiconductor device according to claim 11, wherein Au plating is formed over the surface of each of the electrodes of the second substrate, and the Au plating and the solder are coupled with each other. ### Claim 13 (depends on 7) The method for manufacturing a semiconductor device according to claim 7, wherein, in the step (e), the semiconductor chip is absorbed and held by an absorbing surface of a head of a flip chip bonder, and the semiconductor chip is mounted on the upper surface of the second substrate, and wherein the plane size of the absorbing surface of the head is equal to or smaller than the plane size of the semiconductor chip. ### Claim 14 (depends on 7) The method for manufacturing a semiconductor device according to claim 7, wherein the second substrate is a substrate formed of silicon, and wherein each of the bump electrodes is a columnar electrode formed of an alloy with the main composition of Cu. ### Claim 15 (depends on 7) The method for manufacturing a semiconductor device according to claim 7, wherein the plasm-cleaning in the step (c) is executed by generating plasma by argon gas or oxygen.