# US 2016/0260660 A1 · Electronic device and electronic package thereof

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- Number: US 2016/0260660 A1
- Document ID: US20160260660A1
- Status: Published application
- Kind: A1
- Application number: 14/638,440
- Filed: 2015-03-04
- Published: 2016-09-08
- Earliest claimed: 2015-03-04
- Assignees: Delta Electronics, Inc.
- Applicants: Delta Electronics, Inc.
- Inventors: Shiau Shi LIN; Chia Yen LEE; Hsin Chang TSAI
- Web page: https://patentgrep.com/patent/US20160260660A1

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H05K 1/0206: {by printed thermal vias}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 70/658: {for devices provided for in groups H10D8/00 - H10D48/00}
- H05K 1/112: {directly combined with via connections}
- H10W 72/072: {of bump connectors}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An electronic package is provided, including a substrate and a semiconductor chip. The substrate has a plurality of substrate pads. The semiconductor chip is mounted on the substrate, wherein the semiconductor chip includes a plurality of chip pads electrically connected to the substrate pads of the substrate respectively, and the substrate pads and the chip pads are both trapezoidal.

## Claims

### Claim 1

An electronic package, comprising:
a substrate having a plurality of substrate pads; and
a semiconductor chip mounted on the substrate, wherein the semiconductor chip comprises a plurality of chip pads electrically connected to the substrate pads of the substrate respectively.

### Claim 2 (depends on 1)

The electronic package of claim 1, wherein the substrate pads and the chip pads are both trapezoidal.

### Claim 3 (depends on 1)

The electronic package of claim 1, wherein the semiconductor chip comprises a plurality of active elements electrically connected to the chip pads.

### Claim 4 (depends on 3)

The electronic package of claim 3, wherein the active elements comprise a plurality of power transistors.

### Claim 5 (depends on 1)

The electronic package of claim 1, wherein the substrate comprises a plurality of thermal via holes connected to the substrate pads.

### Claim 6 (depends on 5)

The electronic package of claim 5, wherein more than one of the thermal via holes is connected to each of the substrate pads.

### Claim 7 (depends on 5)

The electronic package of claim 5, wherein each of the substrate pads comprises a wider side and a narrower side opposite the wider side.

### Claim 8 (depends on 7)

The electronic package of claim 7, wherein at least one of the substrate pads has a wider side adjacent to the narrower side of another substrate pad.

### Claim 9 (depends on 7)

The electronic package of claim 7, wherein the thermal via holes are adjoined with the substrate pad in a location that is adjacent to the wider side.

### Claim 10 (depends on 5)

The electronic package of claim 5, wherein heat from the semiconductor chip is conducted to the substrate via the chip pad, the substrate pad, and the thermal via hole along a dissipation path, and the main dissipation path is a straight line.

### Claim 11 (depends on 10)

The electronic package of claim 10, wherein the substrate comprises a plurality of traces, and the traces are perpendicular to the thermal via holes.

### Claim 12 (depends on 1)

The electronic package of claim 1, wherein the semiconductor chip comprises a bottom surface, and the chip pads protrude from the bottom surface.

### Claim 13 (depends on 12)

The electronic package of claim 12, wherein the bottom surface comprises insulation material.

### Claim 14 (depends on 12)

The electronic package of claim 12, wherein the bottom surface comprises SiO2 or SiNx.

### Claim 15 (depends on 1)

The electronic package of claim 1, wherein the shape of the substrate pad is the same as the shape of the corresponding chip pad.

### Claim 16 (depends on 15)

The electronic package of claim 15, wherein the dimensions of the substrate pad are similar to the dimensions of the corresponding chip pad.

### Claim 17 (depends on 1)

The electronic package of claim 1, wherein the substrate comprises a printed circuit board or an interposer.

### Claim 18 (depends on 1)

The electronic package of claim 1, wherein the thickness of the chip pads is greater than 5 μm.

### Claim 19 (depends on 1)

The electronic package of claim 1, wherein the heat from the pads of the semiconductor chip on a top side and a bottom side thereof are transmitted to the substrate pads to be dissipated by a plurality of thermal via holes.

### Claim 20

An electronic device, comprising:
a substrate having a plurality of substrate pads, wherein the substrate comprises a printed circuit board; and
a semiconductor chip mounted on the substrate, wherein the semiconductor chip comprises a plurality of chip pads electrically connected to the substrate pads of the substrate respectively, and the substrate pads and the chip pads are both trapezoidal.

### Claim 21 (depends on 20)

The electronic device of claim 20, wherein the semiconductor chip comprises a plurality of active elements electrically connected to the chip pads.

### Claim 22 (depends on 21)

The electronic device of claim 21, wherein the active elements comprise a plurality of power transistors.

### Claim 23 (depends on 20)

The electronic device of claim 20, wherein the substrate comprises a plurality of thermal via holes connected to the substrate pads.

### Claim 24 (depends on 23)

The electronic device of claim 23, wherein more than one of the thermal via holes is connected to each of the substrate pads.

### Claim 25 (depends on 23)

The electronic device of claim 23, wherein each of the substrate pads comprises a wider side and a narrower side opposite the wider side.

### Claim 26 (depends on 25)

The electronic device of claim 25, wherein at least one of the substrate pads has a wider side adjacent to the narrower side of another substrate pad.

### Claim 27 (depends on 25)

The electronic device of claim 25, wherein the thermal via holes are adjoined with the substrate pad in a location that is adjacent to the wider side.

### Claim 28 (depends on 23)

The electronic device of claim 23, wherein heat from the semiconductor chip is conducted to the substrate via the chip pad, the substrate pad, and the thermal via hole along a dissipation path, and the dissipation path is a straight line.

### Claim 29 (depends on 28)

The electronic device of claim 28, wherein the substrate comprises a plurality of traces, and the traces are perpendicular to the thermal via holes.

### Claim 30 (depends on 20)

The electronic device of claim 20, wherein the semiconductor chip comprises a bottom surface, and the chip pads protrude from the bottom surface.

### Claim 31 (depends on 30)

The electronic device of claim 30, wherein the bottom surface comprises insulation material.

### Claim 32 (depends on 30)

The electronic device of claim 30, wherein the bottom surface comprises SiO2 or SiNx.

### Claim 33 (depends on 20)

The electronic device of claim 20, wherein the shape of the substrate pad is the same as the shape of the corresponding chip pad.

### Claim 34 (depends on 33)

The electronic device of claim 33, wherein the dimensions of the substrate pad are similar to the dimensions of the corresponding chip pad.

### Claim 35 (depends on 20)

The electronic device of claim 20, wherein the thickness of the chip pads is greater than 5 μm.