# US 2016/0260490 A1 · Data storage device and method of driving the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2016/0260490 A1 - Document ID: US20160260490A1 - Status: Published application - Kind: A1 - Application number: 15/063,060 - Filed: 2016-03-07 - Published: 2016-09-08 - Earliest claimed: 2015-03-07 - Assignees: SK hynix Inc.; Seoul National University R&Db Foundation - Applicants: SK hynix Inc.; Seoul National University R&DB Foundation - Inventors: Jong Ho LEE; Ho Jung KANG; Nag Yong CHOI; Byeong Il HAN; Kyoung Jin PARK; Sung Yong CHUNG - Web page: https://patentgrep.com/patent/US20160260490A1 ## CPC - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/3472: {Circuits or methods to verify correct erasure of nonvolatile memory cells whilst erasing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasure} - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/35: with cell select transistors, e.g. NAND - H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A data storage device includes a non-volatile memory device, which includes a memory cell array including a plurality of memory cells and a control circuit. Each of the memory cells includes a channel layer, a charge trap layer on the channel layer, and a control electrode on the charge trap layer, the charge trap layer being shared by the memory cells. The charge trap layer includes program regions respectively disposed below the control electrodes of the memory cells, and charge spread blocking regions, each of which is disposed between two adjacent ones of the program regions and between two adjacent ones of the control electrodes. The control circuit controls the memory cell array so that a potential barrier is generated in the charge spread blocking regions by charging the charge spread blocking regions with charges having the same polarity as that of program charges stored in the program regions. ## Claims ### Claim 1 A non-volatile memory device comprising: a memory cell array including a plurality of memory cells; and a control circuit, wherein each of the plurality of memory cells comprises a channel layer, a charge trap layer disposed over the channel layer, and a control electrode disposed over the charge trap layer, the charge trap layer being shared by the plurality of memory cells in the memory cell array, wherein the charge trap layer comprises: program regions respectively disposed below the control electrodes of the plurality of memory cells; and charge spread blocking regions, each of which is disposed between two adjacent ones of the program regions and between two adjacent ones of the control electrodes, and wherein the control circuit is configured to control the memory cell array so that a potential barrier is generated in the charge spread blocking regions by charging the charge spread blocking regions with charges having the same polarity as that of program charges stored in the program regions. ### Claim 2 (depends on 1) The non-volatile memory device of claim 1, wherein the memory cell array comprises a plurality of memory strings, each memory string including the plurality of memory cells that are connected to one another in series. ### Claim 3 (depends on 1) The non-volatile memory device of claim 1, wherein the channel layer is provided by a semiconductor pillar extending in a direction perpendicular to a main surface of a substrate, a first insulation layer, the charge trap layer, and a second insulation layer are sequentially disposed on sidewalls of the semiconductor pillar, and the memory cell array is a 3-dimensional memory cell array. ### Claim 4 (depends on 3) The non-volatile memory device of claim 3, wherein the first insulation layer is a tunneling insulation layer, and the second insulation layer is a blocking insulation layer. ### Claim 5 (depends on 1) The non-volatile memory device of claim 1, wherein the control circuit performs a pre-programming operation for charging the program regions and the charge spread blocking regions of the charge trap layer with charges having a same polarity by applying a program voltage to the control electrodes of the plurality of memory cells simultaneously. ### Claim 6 (depends on 5) The non-volatile memory device of claim 5, wherein the pre-programming operation is performed by charging the charge spread blocking regions of the charge trap layer using a fringing electric field. ### Claim 7 (depends on 5) The non-volatile memory device of claim 5, wherein the pre-programming operation is performed for two or more pages, one or more strings, or one or more blocks in the memory cell array, or for the entire memory cell array. ### Claim 8 (depends on 1) The non-volatile memory device of claim 1, wherein the charge spread blocking regions are charged by the injection of electric charge carriers from the channel layer, Fowler-Nordheim tunnelling of electric charge carriers from a source or a drain of the channel layer, or Fowler-Nordheim tunnelling of electric charge carriers from the channel layer. ### Claim 9 (depends on 1) The non-volatile memory device of claim 1, wherein the control circuit performs an erasing operation on the plurality of memory cells to preserve the potential barrier. ### Claim 10 (depends on 9) The non-volatile memory device of claim 9, wherein a width of the charge spread blocking region is greater than a width of the program region. ### Claim 11 (depends on 1) The non-volatile memory device of claim 1, wherein the control circuit performs a two-step erasing operation comprising: a first erasing step for erasing data of even-numbered memory cells from among the plurality of memory cells; and a second erasing step for erasing data of odd-numbered memory cells from among the plurality of memory cells, the second erasing step being performed separately in time from the first erasing step. ### Claim 12 (depends on 11) The non-volatile memory device of claim 11, wherein, if the two-step erasing operation is performed a number of times, an order of performing the first erasing step and the second erasing step is changed each time the two-step erasing operation is performed. ### Claim 13 (depends on 11) The non-volatile memory device of claim 11, wherein, before the two-step erasing operation is performed, the control circuit performs a pre-programming operation for charging the program regions and the charge spread blocking regions of the charge trap layer with charges having a same polarity by applying a program voltage to the control electrodes of the plurality of memory cells simultaneously. ### Claim 14 (depends on 13) The non-volatile memory device of claim 13, wherein, when the two-step erasing operation is performed a number of times, the pre-programming operation is performed before each two-step erasing operation is performed. ### Claim 15 (depends on 13) The non-volatile memory device of claim 13, further comprising a counter for counting a number of times that the two-step erasing operation is performed, wherein the control circuit receives information regarding the number of times that the two-step erasing operation is performed from the counter and, when the two-step erasing operation is repeated a specific number of times, performs the pre-programming operation before the specific number of times the two-step erasing operation is performed. ### Claim 16 (depends on 13) The non-volatile memory device of claim 13, wherein, in case of programming one or more selected memory cells according to a program after erase (PAE) scheme, the pre-programming operation and the two-step erasing operation following the pre-programming operation are performed before a program operation is performed on the selected memory cells, and wherein if data is erased from a predetermined area comprising some of the plurality of memory cells, one or more strings, one or more pages, or one or more blocks, the pre-programming operation and the two-step erasing operation are performed with respect to the predetermined area. ### Claim 17 (depends on 13) The non-volatile memory device of claim 13, wherein the pre-programming operation and the two-step erasing operation are performed to initialize the plurality of memory cells. ### Claim 18 A method of driving a non-volatile memory device, the method comprising: a first erasing step for erasing data of even-numbered memory cells among a plurality of memory cells; and a second erasing step for erasing data of odd-numbered memory cells from among the plurality of memory cells, the second erasing step being performed separately in time from the first erasing step, wherein the plurality of memory cells shares a charge trap layer, and wherein the charge trap layer comprises program regions respectively allocated to the plurality of memory cells and charge spread blocking regions, each of the charge spread blocking regions being disposed between two adjacent ones of the program regions. ### Claim 19 (depends on 18) The method of claim 18, wherein the plurality of memory cells is included in a memory string. ### Claim 20 (depends on 18) The method of claim 18, wherein, if the two-step erasing operation is performed a number of times, a sequence for performing the first erasing step and the second erasing step is changed each time the two-step erasing operation is performed. ### Claim 21 (depends on 18) The method of claim 18, further comprising performing a pre-programming operation on the plurality of memory cells before the two-step erasing operation, wherein the pre-programming operation is performed to charge the charge spread blocking regions with charges having the same polarity as that of program charges stored in the program regions. ### Claim 22 (depends on 21) The method of claim 21, wherein, in the pre-programming operation, the program regions and the charge spread blocking regions of the charge trap layer are simultaneously charged with charges having a same polarity by applying a program voltage to control electrodes of the plurality of memory cells simultaneously. ### Claim 23 (depends on 21) The method of claim 21, wherein the pre-programming operation is performed for at least two pages, one or more strings, or one or more blocks of a memory cell array including the plurality of memory cells, or for the entire memory cell array. ### Claim 24 (depends on 21) The method of claim 21, wherein, when the two-step erasing operation is performed a number of times, the pre-programming operation is performed prior to each time the two-step erasing operation is performed. ### Claim 25 (depends on 21) The method of claim 21, wherein the pre-programming operation is performed one time whenever the two-step erasing operation is repeated a specific number of times. ### Claim 26 A method of driving a non-volatile memory device, the method comprising performing a pre-programming operation on a plurality of memory cells to charge spread blocking regions with charges having the same polarity as that of program charges stored in program regions, wherein the plurality of memory cells shares a charge trap layer, and wherein the charge trap layer comprises the program regions respectively allocated to the plurality of memory cells and the charge spread blocking regions, each of the charge spread blocking regions being disposed between two adjacent ones of the program regions. ### Claim 27 (depends on 26) The method of claim 26, wherein the pre-programming operation is performed for at least two pages, one or more strings, or one or more blocks of a memory cell array including the plurality of memory cells, or for the entire memory cell array. ### Claim 28 (depends on 26) The method of claim 26, further comprising performing a two-step erasing operation after the pre-programming operation is performed, wherein the two-step erasing operation comprises: a first erasing step for erasing data of even-numbered memory cells from among the plurality of memory cells; and a second erasing step for erasing data of odd-numbered memory cells from among the plurality of memory cells, the second erasing step being performed separately in time from the first erasing step, wherein, in case of programming one or more memory cells selected by using a program after erase (PAE) scheme, the pre-programming operation and the two-step erasing operation are performed before a program operation is performed on the selected memory cells, and wherein if data is erased from a predetermined area comprising some of the plurality of memory cells, one or more strings, one or more pages, or one or more blocks, the pre-programming operation and the two-step erasing operation are performed with respect to the predetermined area. ### Claim 29 (depends on 26) The method of claim 26, further comprising performing a two-step erasing operation after the pre-programming operation is performed, wherein the two-step erasing operation comprises: a first erasing step for erasing data of even-numbered memory cells from among the plurality of memory cells; and a second erasing step for erasing data of odd-numbered memory cells from among the plurality of memory cells, the second erasing step being performed separately in time from the first erasing step, and wherein the pre-programming operation and the two-step erasing operation are performed to initialize the plurality of memory cells.