# US 2016/0260484 A1 · Semiconductor memory device and operating method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2016/0260484 A1 - Document ID: US20160260484A1 - Status: Published application - Kind: A1 - Application number: 14/812,518 - Filed: 2015-07-29 - Published: 2016-09-08 - Earliest claimed: 2015-03-06 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Kyoung Hoon LIM; Min Kyu LEE - Web page: https://patentgrep.com/patent/US20160260484A1 ## CPC - G11C 16/10: Programming or data input circuits - G11C 16/24: Bit-line control circuits - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Disclosed are a semiconductor memory device, and an operating method thereof. The semiconductor memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program pulse application operation and a verification operation on the memory cell array; a pass/fail check circuit configured to output a pass/fail signal according to a result of the verification operation; and a control logic configured to control the peripheral circuit to perform the program pulse application operation and the verification operation such that two or more program pulses are continuously applied during the program pulse application operation, and first and second verification operations are continuously performed during the verification operation. ## Claims ### Claim 1 A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program pulse application operation and a verification operation on the memory cell array; a pass/fail check circuit configured to output a pass/fail signal according to a result of the verification operation; and a control logic configured to control the peripheral circuit to perform the program pulse application operation and the verification operation such that two or more program pulses are continuously applied during the program pulse application operation, and first and second verification operations are continuously performed during the verification operation. ### Claim 2 (depends on 1) The semiconductor memory device of claim 1, wherein the peripheral circuit includes a voltage generating unit, which generates program pulses gradually increasing by a step voltage during the program pulse application operation, generates a first verification voltage during the first verification operation, and generates a second verification voltage larger than the first verification voltage by the step voltage during the second verification operation. ### Claim 3 (depends on 1) The semiconductor memory device of claim 1, wherein the peripheral circuit includes a read and write circuit, which is electrically coupled with bit lines of the memory cell array, controls potential levels of the bit lines according to program data during the program pulse application operation, and senses potentials of the bit lines and outputs a verification signal during the first and second verification operations. ### Claim 4 (depends on 3) The semiconductor memory device of claim 3, wherein the read and write circuit includes a plurality of page buffers electrically coupled with the bit lines, respectively, and the plurality of page buffers performs the second verification operation without performing a discharge operation and a precharge operation on the bit lines after completing the first verification operation. ### Claim 5 (depends on 3) The semiconductor memory device of claim 3, wherein the pass/fail check circuit outputs the pass/fail signal according to a number of failed memory cells during the first verification operation, and the pass/fail signal according to the number of failed memory cells during the second verification operation according to the verification signal. ### Claim 6 (depends on 1) The semiconductor memory device of claim 1, wherein when it is determined that the first verification operation is failed as results of the first and second verification operations, the control logic controls the peripheral circuit to perform the program pulse application operation by continuously applying a first program pulse obtained by increasing the previous program pulse by a step voltage and a second program pulse obtained by increasing the first program pulse by the step voltage. ### Claim 7 (depends on 1) The semiconductor memory device of claim 1, wherein when it is determined that the first verification operation passes and the second verification operation is failed as results of the first and second verification operations, the control logic controls the peripheral circuit to continuously apply a first program pulse obtained by increasing the previous program pulse by a step voltage and a second program pulse obtained by increasing the first program pulse by the step voltage. ### Claim 8 (depends on 7) The semiconductor memory device of claim 7, wherein when it is determined that the second verification operation passes as results of the first and second verification operations, the control logic controls the peripheral circuit to perform the program pulse application operation of applying a third program pulse obtained by increasing a previous program pulse by the step voltage and then terminating a program operation. ### Claim 9 A method of operating a semiconductor memory device, comprising: applying a program pulse to selected memory cells among a plurality of memory cells; continuously performing first and second verification operations using different first and second verification voltages; and when it is determined that the first verification operation has failed, continuously applying new program pulses obtained by increasing a previously applied program pulse by a step voltage and two times of the step voltage to the selected memory cells, and then re-performing from the first and second verification operations. ### Claim 10 (depends on 9) The method of claim 9, wherein the second verification voltage is a voltage larger than the first verification voltage by the step voltage. ### Claim 11 (depends on 9) The method of claim 9, further comprising: when it is determined that the first verification operation passes and the second verification operation has failed as results of the first and second verification operations, continuously applying the new program pulses obtained by increasing a last applied program pulse by the step voltage and two times of the step voltage to the selected memory cells, and then terminating a program operation. ### Claim 12 (depends on 11) The method of claim 11, further comprising: when it is determined that the second verification operation passes as results of the first and second verification operations, applying an other new program pulse obtained by increasing the last applied program pulse by the step voltage. ### Claim 13 A method of operating a semiconductor memory device, comprising: applying a program pulse to selected memory cells among a plurality of memory cells; continuously performing first and second verification operations using different first and second verification voltages; and when it is determined that the first verification operation has failed, continuously applying new program pulses obtained by increasing a previously applied program pulse by a step voltage and two times of the step voltage to the selected memory cells, and then re-performing from the first and second verification operations, wherein after the applying of the program pulse, a discharge operation and a precharge operation of a bit line electrically coupled to the selected memory cells are performed before performing the first verification operation, and the discharge operation and the precharge operation of the bit line are skipped when the first verification operation is completed and then the second verification operation is performed. ### Claim 14 (depends on 13) The method of claim 13, wherein the second verification voltage is a voltage larger than the first verification voltage by the step voltage. ### Claim 15 (depends on 13) The method of claim 13, further comprising: when it is determined that the first verification operation passes and the second verification operation has failed as results of the first and second verification operations, continuously applying the new program pulses obtained by increasing a last applied program pulse by the step voltage and two times of the step voltage to the selected memory cells, and then terminating a program operation. ### Claim 16 (depends on 15) The method of claim 15, further comprising: when it is determined that the second verification operation passes as the results of the first and second verification operations, applying an other new program pulse obtained by increasing the last applied program pulse by the step voltage. ### Claim 17 (depends on 1) The semiconductor memory device of claim 1, wherein when a number of counted memory cells is greater than a permitted number, the pass/fail check circuit outputs a fail signal. ### Claim 18 (depends on 1) The semiconductor memory device of claim 1, wherein when a number of counted memory cells is less than a permitted number, the pass/fail check circuit outputs a pass signal. ### Claim 19 (depends on 1) The semiconductor memory device of claim 1, wherein the control logic controls a voltage generating unit to verify a first verification voltage and a second verification voltage. ### Claim 20 (depends on 19) The semiconductor memory device of claim 19, wherein the second verification voltage is a target threshold voltage for programming the plurality of memory cells.