# US 2016/0260477 A1 · Variable resistive memory device and method of operating the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2016/0260477 A1
- Document ID: US20160260477A1
- Status: Published application
- Kind: A1
- Application number: 14/798,795
- Filed: 2015-07-14
- Published: 2016-09-08
- Earliest claimed: 2015-03-04
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Ki Myung KYUNG
- Web page: https://patentgrep.com/patent/US20160260477A1

## CPC

- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 13/0023: {Address circuits or decoders}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0028: {Word-line or row circuits}
- G11C 13/0061: {Timing circuits or methods}
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 2213/79: Array wherein the access device being a transistor
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A variable resistive memory device may include a memory region and controller. The memory region may include a plurality of unit memory cells each electrically connected between a word line and a bit line. The controller may perform a driving operation of the word line in response to a read command. The controller may perform a driving operation of a bit line to output cell data through the bit line substantially simultaneously with the driving operation of the word line. Each of the unit memory cell may include a variable resistive material.

## Claims

### Claim 1

A variable resistive memory device comprising:
a memory region including a plurality of unit memory cells each electrically connected between a word line and a bit line; and
a controller configured to perform a driving operation of the word line in response to a read command simultaneously with a driving operation of the bit line for outputting cell data through the bit line,
wherein each of the unit memory cells include a variable resistive material.

### Claim 2 (depends on 1)

The variable resistive memory device of claim 1, wherein the variable resistive material of each unit memory cell is coupled is between a bit line and a word line.

### Claim 3 (depends on 1)

The variable resistive memory device of claim 1, wherein the driving operation of the bit line comprises pre-charging the bit line, stabilizing the bit line, and sensing and outputting the cell data.

### Claim 4 (depends on 1)

The variable resistive memory device of claim 1, wherein the controller controls a time for driving the word line with substantially the same time as for driving the bit line.

### Claim 5 (depends on 1)

The variable resistive memory device of claim 1, wherein the controller discharges the bit line for a predetermined time simultaneously with the driving operation of the word line before performing the driving operation of the bit line.

### Claim 6 (depends on 5)

The variable resistive memory device of claim 5, wherein the controller operates discharging the bit line and driving the bit line during the driving of the word line.

### Claim 7 (depends on 1)

The variable resistive memory device of claim 1, further comprising:
a release circuit electrically connected to the bit line to supply a release voltage to the bit line in response to a release signal.

### Claim 8 (depends on 7)

The variable resistive memory device of claim 7, wherein the release circuit is enabled for a predetermined time simultaneously with the driving operation of the word line before driving the bit line.

### Claim 9 (depends on 7)

The variable resistive memory device of claim 7, wherein the release circuit is enabled for supplying the release voltage to the bit line and driving the bit line during the driving of the word line.

### Claim 10 (depends on 7)

The variable resistive memory device of claim 7, wherein the release voltage comprises a ground voltage or a read voltage.

### Claim 11 (depends on 7)

The variable resistive memory device of claim 7, wherein the release circuit includes a MOS transistor, the MOS transistor coupled between the bit line and a supply terminal of the release voltage and having a gate configured to receive the release signal.

### Claim 12 (depends on 11)

The variable resistive memory device of claim 11, further comprising:
a local bit line switch coupled to the release circuit through a local bit line and coupled to the unit memory cells through respective bit lines; and
a global bit line switch coupled to the local bit line and configured to apply a predetermined level of a pre-charge voltage to a bit line through a global bit line coupled to the global bit line switch,
wherein the MOS transistor has a channel length longer than a channel length of a switching element of the local bit line switch and the global bit line switch.

### Claim 13 (depends on 11)

The variable resistive memory device of claim 11, further comprising:
cell blocks located in the memory region, the cell blocks including the unit memory cells; and
a local bit line switch block located at one side of each cell block;
wherein the release circuit is located within a region of the local bit line switch block.

### Claim 14 (depends on 1)

The variable resistive memory device of claim 1, wherein the controller simultaneously disables the word line and the bit line after the driving operation of the word line and the driving operation of the bit line.

### Claim 15

A method of operating a variable resistive memory device, the variable resistive memory device including a memory region and a controller, the memory region including a plurality of unit memory cells each electrically connected between a word line and a bit line and including a variable resistive material, and the controller for controlling the memory region, the method comprising:
performing a driving operation of the word line in response to a read command by the controller,
wherein the driving operation of the word line is performed simultaneously with a driving operation of the bit line for outputting cell data through the bit line.

### Claim 16 (depends on 15)

The method of claim 15, wherein the driving operation of the bit line comprises pre-charging the bit line, stabilizing the bit line, and sensing and outputting the cell data.

### Claim 17 (depends on 15)

The method of claim 15, wherein the controller controls a time for driving the word line with substantially the same time as for driving the bit line.

### Claim 18 (depends on 15)

The method of claim 15, wherein the controller discharges the bit line for a predetermined time simultaneously with the driving operation of the word line before performing the driving operation of the bit line.

### Claim 19 (depends on 18)

The method of claim 18, wherein the controller operates discharging the bit line and driving the bit line during the driving of the word line.

### Claim 20 (depends on 15)

The method of claim 15, further comprising:
supplying a release voltage to the bit line for a predetermined time simultaneously with the driving operation of the word line before performing the driving operation of the bit line by the controller.

### Claim 21 (depends on 20)

The method of claim 20, wherein the controller controls supplying the release voltage to the bit line and driving the bit line during the driving of the word line.

### Claim 22 (depends on 20)

The method of claim 20, wherein the release voltage comprises a ground voltage or a read voltage.

### Claim 23 (depends on 15)

The method of claim 15, wherein the controller simultaneously disables the word line and the bit line after the driving operation of the word line and the driving operation of the bit line.