# US 2016/0259756 A1 · Circuits and methods for inter-processor communication

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- Number: US 2016/0259756 A1
- Document ID: US20160259756A1
- Status: Published application
- Kind: A1
- Application number: 14/638,692
- Filed: 2015-03-04
- Published: 2016-09-08
- Earliest claimed: 2015-03-04
- Assignees: Xilinx, Inc.
- Applicants: Xilinx, Inc.
- Inventors: Sagheer Ahmad; Soren Brinkmann
- Web page: https://patentgrep.com/patent/US20160259756A1

## CPC

- G06F 15/167: using a common memory, e.g. mailbox
- G06F 12/1425: {the protection being physical, e.g. cell, word, block}
- G06F 13/1673: {using buffers}
- G06F 13/24: using interrupt (G06F13/32 takes precedence)
- G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus}
- G06F 15/17: using an input/output type connection, e.g. channel, I/O port
- G06F 15/17337: {Direct connection machines, e.g. completely connected computers, point to point communication networks (coupling between buses G06F13/4004)}
- G06F 2212/1052: Security improvement
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Various example implementations are directed to circuits and methods for communicating between disparate processor circuits. According to an example implementation, a circuit arrangement includes a plurality of processor circuits and an inter-processor communication circuit. The inter-processor communication circuit is configured to provide, for each pair of the processor circuits, a respective communication channel between the pair of processor circuits. The inter-processor communication circuit includes a plurality of buffers including a respective first buffer and a respective second buffer for each communication channel. An access control circuit included in the inter-processor communication circuit is configured to restrict write access to the respective first buffer to the first processor circuit and restrict write access to the respective second buffer to the second processor circuit.

## Claims

### Claim 1

A system, comprising:
a plurality of processor circuits; and
an inter-processor communication circuit coupled to the plurality of processor circuits and configured to provide, for each pair of the processor circuits, a respective communication channel between a first processor circuit of the pair to a second processor circuit of the pair, wherein the inter-processor communication circuit includes:
a plurality of buffers including for each respective communication channel, a respective first buffer and a respective second buffer; and
an access control circuit coupled to the plurality of buffers and configured to, for the respective communication channel between the first processor circuit to the second processor circuit:
restrict write access to the first buffer to the first processor circuit; and
restrict write access to the second buffer to the second processor circuit.

### Claim 2 (depends on 1)

The system of claim 1, wherein for the respective communication channel the access control circuit is further configured to restrict read access to the first and second buffers to the first and second processor circuits.

### Claim 3 (depends on 1)

The system of claim 1, wherein:
the respective communication channel between the first and second processor circuits is bidirectional;
the plurality of processor circuits includes N processor circuits; and
the plurality of buffers includes (N2+N)/2 buffers.

### Claim 4 (depends on 1)

The system of claim 1, wherein:
for each of the pairs of the processor circuits, the respective communication channel between the first and second processor circuits is a communication channel from the first processor circuit to the second processor circuit; and
the inter-processor communication circuit is further configured to provide a second communication channel from the second processor circuit to the first processor circuit.

### Claim 5 (depends on 4)

The system of claim 4, wherein:
the plurality of processor circuits includes N processor circuits; and
the plurality of buffers includes (2N2+2N) buffers.

### Claim 6 (depends on 1)

The system of claim 1, wherein for each of the pairs of the processor circuits, the respective first processor circuit is configured to, in response to writing a message to the first buffer, prompt the respective second processor to read the message from the first buffer.

### Claim 7 (depends on 6)

The system of claim 6, wherein the prompting by the first processor circuit includes providing setting a first interrupt.

### Claim 8 (depends on 7)

The system of claim 7, wherein for each of the pairs of the processor circuits, the respective second processor circuit is configured to read the message from the respective first buffer in response to the first interrupt.

### Claim 9 (depends on 8)

The system of claim 8, wherein the respective second processor circuit is further configured to, in response to the message read from the respective first buffer:
write a response message to the respective second buffer; and
prompt the respective first processor circuit to read the response message from the second buffer.

### Claim 10 (depends on 9)

The system of claim 9, wherein the prompting of the respective first processor circuit by the respective second processor circuit includes clearing the first interrupt.

### Claim 11 (depends on 9)

The system of claim 9, wherein the prompting of the respective first processor circuit by the respective second processor circuit setting a second interrupt.

### Claim 12 (depends on 1)

The system of claim 1, wherein:
the plurality of buffers are located at respective memory addresses of a memory; and
the access control circuit is configured to process access requests to read or write from the memory.

### Claim 13 (depends on 12)

The system of claim 12, wherein the access control circuit is configured to, in response to one of the access requests, determine whether or not access should be allowed based on a source address indicated in the access request, a destination address indicated in the access request, and a permissions table indicating access permissions for each of the plurality of buffers.

### Claim 14 (depends on 13)

The system of claim 13, wherein the permissions table is stored in the memory.

### Claim 15

A method for communication between a plurality of processor circuits, comprising, for at least one pair of the plurality of processor circuits:
restricting write access to a respective first buffer for the pair to a first processor circuit of the pair;
restricting write access to a respective second buffer for the pair to a second processor circuit of the pair;
communicating messages from the first processor circuit of the pair to the second processor circuit of the pair via the respective first buffer; and
communicating messages from the second processor circuit of the pair to the first processor circuit of the pair via the respective second buffer.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
restricting read access to the respective first and second buffers to the first and second processor circuits of the pair; and
wherein the communicating of the messages from the first processor circuit to the second processor circuit includes:
using the first processor circuit of the pair,
writing a first message to the respective first buffer, and
prompting the second processor circuit of the pair to read the first message from the respective first buffer; and
using the second processor circuit of the pair, retrieving the first message from the respective first buffer in response to the prompting by the first processor circuit.

### Claim 17 (depends on 16)

The method of claim 16, wherein the communicating of the messages from the second processor circuit to the first processor circuit includes:
using the second processor circuit of the pair,
writing a second message to the respective second buffer in response to reading the first message from the respective first buffer, and
prompting the first processor circuit of the pair to read the second message from the respective second buffer; and
using the first processor circuit of the pair, reading the second message from the respective first buffer in response to the prompting by the second processor circuit of the pair.

### Claim 18 (depends on 17)

The method of claim 17, wherein:
the restricting read and write access to the first and second buffers is performed using an access control circuit included in an inter-processor communication circuit; and
the writing of the message to the first and second buffers, and the reading of the messages from the first and second buffers communicates the messages between the first and second processor circuits and the first and second buffers via the inter-processor communication circuit.

### Claim 19 (depends on 17)

The method of claim 17, wherein:
the prompting of the second processor circuit includes setting a first interrupt; and
the prompting of the first processor circuit includes setting a second interrupt.

### Claim 20 (depends on 17)

The method of claim 17, wherein:
the prompting of the second processor circuit includes setting a first interrupt; and
the prompting of the first processor circuit includes clearing the first interrupt.