# US 2016/0259686 A1 · Updating reliability data

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- Number: US 2016/0259686 A1
- Document ID: US20160259686A1
- Status: Published application
- Kind: A1
- Application number: 15/157,042
- Filed: 2016-05-17
- Published: 2016-09-08
- Earliest claimed: 2012-10-11
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Saeed Sharifi Tehrani; Nicholas J. Richardson
- Web page: https://patentgrep.com/patent/US20160259686A1

## CPC

- G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- H03M 13/1108: {Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping}
- H03M 13/1137: {Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel}
- H03M 13/114: {Shuffled, staggered, layered or turbo decoding schedules}
- H03M 13/116: {Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices}
- H03M 13/6577: {Representation or format of variables, register sizes or word-lengths and quantization}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.

## Claims

### Claim 1

An apparatus, comprising:
a memory device;
a reliability circuit coupled to the memory device and configured to receive hard data from the memory device and to determine reliability data assigned thereto, the reliability data comprising a first reliability data value in response to the hard data comprising a first value or comprising a second reliability data value in response to the hard data comprising a second value;
an error correction circuit coupled to the reliability circuit and configured to receive the hard data and the reliability data from the reliability circuit, wherein the error correction circuit is further configured to:
iteratively compute parity data for the hard data; and
increment or decrement the reliability data once per L-number of layers of parity data, wherein one iteration includes a plurality of layers of parity data.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the error correction circuit includes:
a plurality of check nodes configured to iteratively compute the parity data for the hard data; and
a plurality of variable nodes configured to update the reliability data.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the error correction circuit includes a plurality of check nodes configured to iteratively compute the parity data for the hard data and to increment or decrement the reliability data.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the error correction circuit is coupled to a host and configured to provide the hard data to the host in response to either a particular number of iterations being performed or in response to a syndrome check on the hard data being correct.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the reliability circuit comprises a log likelihood ratio (LLR) circuit and the error correction circuit comprises a low density parity check (LDPC) circuit.

### Claim 6

An apparatus, comprising:
a plurality of circulant memories;
a plurality of check nodes coupled to the plurality of circulant memories according to a parity check code; and
wherein the plurality of circulant memories are each configured to provide respective hard data and respective reliability data to those of the plurality of check nodes coupled thereto; and
wherein the plurality of check nodes are each configured to compute parity data for received hard data, update received reliability data based at least in part on the parity data, and send the parity data and updated reliability data to those of the circulant memories coupled thereto.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the apparatus includes:
an input coupled to the plurality of circulant memories, the input configured to provide hard data and reliability data thereto; and
an output coupled to the plurality of circulant memories and configured to receive hard data therefrom; and
wherein the plurality of check nodes are configured to perform a syndrome check based on the hard data received from the plurality of circulant memories.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the input is configured to provide semi-soft data to the circulant memories in response to the syndrome check failing for the hard data.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the input is configured to provide full-soft data in response to the syndrome check failing for the semi-soft data.

### Claim 10

A method, comprising:
determining, with a reliability circuit, reliability data assigned to hard data received from a memory device, the reliability data comprising a first reliability data value in response to the hard data comprising a first value or comprising a second reliability data value in response to the hard data comprising a second value;
iteratively computing parity data for the hard data received from the reliability circuit with an error correction circuit; and
incrementing or decrementing the reliability data received from the reliability circuit with the error correction circuit once per L-number of layers of parity data, wherein one iteration includes a plurality of layers of parity data.

### Claim 11 (depends on 10)

The method of claim 10, wherein iteratively computing the parity data comprises iteratively computing the parity data with a plurality of check nodes of the error correction circuit.

### Claim 12 (depends on 11)

The method of claim 11, wherein updating the reliability data comprises updating the reliability data with a plurality of variable nodes of the error correction circuit.

### Claim 13 (depends on 10)

The method of claim 10, wherein iteratively computing the parity data and incrementing or decrementing the reliability data comprises iteratively computing the parity data and incrementing or decrementing the reliability data with a plurality of check nodes of the error correction circuit.

### Claim 14 (depends on 10)

The method of claim 10, wherein the method includes the error correction circuit providing the hard data to a host in response to either a particular number of iterations being performed or in response to a syndrome check on the hard data being correct.

### Claim 15

A method, comprising:
providing, from each of a plurality of circulant memories, respective hard data and respective reliability data to those of a plurality of check nodes coupled thereto;
computing parity data for received hard data with each of a plurality of check nodes;
updating received reliability data based at least in part on the parity data with each of a plurality of check nodes; and
sending, from each of the plurality of check nodes, the parity data and updated reliability data to those of the circulant memories coupled thereto.

### Claim 16 (depends on 15)

The method of claim 15, wherein the method includes providing hard data and reliability data from an input of the plurality of circulant memories.

### Claim 17 (depends on 16)

The method of claim 16, wherein the method includes receiving hard data from an output of the plurality of circulant memories.

### Claim 18 (depends on 17)

The method of claim 17, wherein the method includes performing a syndrome check based on the hard data received from the plurality of circulant memories with the plurality of check nodes.

### Claim 19 (depends on 18)

The method of claim 18, wherein the method includes providing semi-soft data to the circulant memories in response to the syndrome check failing for the hard data.

### Claim 20 (depends on 19)

The method of claim 19, wherein the method includes providing full-soft data in response to the syndrome check failing for the semi-soft data.