# US 2016/0259685 A1 · Memory system and read reclaim method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2016/0259685 A1 - Document ID: US20160259685A1 - Status: Published application - Kind: A1 - Application number: 15/156,912 - Filed: 2016-05-17 - Published: 2016-09-08 - Earliest claimed: 2012-10-05 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: YOUNG WOO JUNG; HWAN-CHUNG KIM; KYOUNGKUY PARK; EUNJU PARK; BONG-GWAN SEOL - Web page: https://patentgrep.com/patent/US20160259685A1 ## CPC - G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)} - G06F 11/1072: {in multilevel memories} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/0253: {Garbage collection, i.e. reclamation of unreferenced memory} - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 11/5671: {using charge trapping in an insulator} - G11C 16/10: Programming or data input circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory system includes a nonvolatile memory device including a first memory area formed of memory blocks which store n-bit data per cell and a second memory area formed of memory blocks which store m-bit data per cell, where n and m are different integers, and a memory controller configured to control the nonvolatile memory device. The memory controller is configured to execute a read operation, and to execute a read reclaim operation in which valid data of a target memory block of the second memory area is transferred to one or more memory blocks of the first memory area, the target memory block selected during the read operation. The read reclaim operation is processed as complete when all the valid data of the target memory block is transferred to the one or more memory blocks of the first memory area. ## Claims ### Claim 1 A memory system comprising: a nonvolatile memory device including a plurality of first memory cells and a plurality of second memory cells, each of the plurality of first memory cells being configured to store 3-bit data, each of the plurality of second memory cells being configured to store 1-bit data; and a controller configured to control the nonvolatile memory device to perform a read operation, a program operation and a re-program operation, wherein the controller is configured to perform an error checking and correction (ECC) operation on first data to generate ECC-performed first data, the first data being read from a first portion of the plurality of first memory cells at a first voltage level, the controller is configured to perform a read retry operation and the ECC operation on second data to generate ECC-performed second data when a number of error bits of the ECC-performed first data exceeds a threshold correctable by the ECC operation, the read retry operation including reading the second data stored in the first portion of the plurality of first memory cells at a second voltage level that is different from the first voltage level, the second data being read from the first portion of the plurality of first memory cells, the controller is configured to output to the nonvolatile memory device first page data including either the ECC-performed first data or the ECC-performed second data, the nonvolatile memory device is configured to program the first page data in a first portion of the plurality of second memory cells, the nonvolatile memory device is configured to read the programmed first page data in the first portion of the plurality of second memory cells, the nonvolatile memory device is configured to program in a second portion of the plurality of first memory cells the programmed first page data that is read at a first time from the first portion of the plurality of second memory cells, and the nonvolatile memory device is configured to re-program in the second portion of the plurality of first memory cells the programmed first page data that is read at a second time from the first portion of the plurality of second memory cells. ### Claim 2 (depends on 1) The memory system of claim 1, wherein the first time is different from the second time. ### Claim 3 (depends on 1) The memory system of claim 1, wherein the controller is configured to program in the second portion of the plurality of first memory cells the first page data that is read at the first time from the first portion of the plurality of second memory cells, without performing the ECC operation on the first page data. ### Claim 4 (depends on 1) The memory system of claim 1, wherein the controller is configured to perform the read retry operation and the ECC operation on third data that is read from the first portion of the plurality of first memory cells. ### Claim 5 (depends on 1) The memory system of claim 1, wherein the controller is configured to perform the ECC operation on fourth data that is read from the second portion of the plurality of first memory cells. ### Claim 6 (depends on 5) The memory system of claim 5, wherein the first portion of the plurality of first memory cells and the second portion of the plurality of first memory cells are included in the same memory block. ### Claim 7 (depends on 5) The memory system of claim 5, wherein the fourth data is included in second page data that is output to the nonvolatile memory device from the controller. ### Claim 8 (depends on 7) The memory system of claim 7, wherein each of the first page data and the second page data is valid page data. ### Claim 9 (depends on 1) The memory system of claim 1, wherein the controller is configured to read and program the first page data in the first portion of the plurality of second memory cells after the controller processes a request by an external device. ### Claim 10 (depends on 9) The memory system of claim 9, wherein the first page data and the second page data are output to the nonvolatile memory device from the controller within a predetermined time period. ### Claim 11 (depends on 1) The memory system of claim 1, wherein the nonvolatile memory device includes a memory cell array having a vertical or stack-type three-dimensional array structure. ### Claim 12 A memory system comprising: a nonvolatile memory device including: a first group of flash memory cells formed of a plurality of first memory blocks, each of the first group of flash memory cells being configured to store 1-bit data per cell; and a second group of flash memory cells formed of a plurality of second memory blocks, each of the second group of flash memory cells being configured to store 3-bits data per cell; and a memory controller configured to control the nonvolatile memory device, wherein the memory controller is configured to perform a read reclaim operation to transfer valid data stored in one of the plurality of second memory blocks to one or more memory blocks of the plurality of first memory blocks, the read reclaim operation is performed on a first portion of the valid data at a first time, and is performed on a second portion of the valid data at a second time that is different from the first time, and the memory controller is configured to perform one or more program operations to transfer a third portion of the valid data that is read from the one or more memory blocks of the plurality of first memory blocks to another of the plurality of second memory blocks other than the one of the plurality of second memory blocks. ### Claim 13 (depends on 12) The memory system of claim 12, wherein the memory controller is configured to perform the one or more program operations to transfer the third portion of the valid data to another of the plurality of second memory blocks, without performing an ECC operation on the third portion of the valid data. ### Claim 14 (depends on 12) The memory system of claim 12, wherein each of the one or more program operations is a three-step programming operation. ### Claim 15 (depends on 14) The memory system of claim 14, wherein the three-step programming operation includes a first program step and a second program step that occurs after the first program step, a second threshold voltage distribution corresponding to the second program step is narrower than a first threshold voltage distribution corresponding to the first program step. ### Claim 16 (depends on 12) The memory system of claim 12, wherein the read reclaim operation includes a read retry operation on at least a portion of the valid data. ### Claim 17 (depends on 16) The memory system of claim 16, wherein the read reclaim operation is performed during a first time period and a second time period, and the first time period and the second time period are separated to each other. ### Claim 18 (depends on 12) The memory system of claim 12, wherein the nonvolatile memory device includes a memory cell array having a vertical or stack-type three-dimensional array structure. ### Claim 19 A method of operating a nonvolatile memory system including a controller and a nonvolatile memory device, the nonvolatile memory device including a plurality of first memory cells and a plurality of second memory cells, each of the plurality of first memory cells being configured to store 3-bit data, each of the plurality of second memory cells being configured to store 1-bit data, the method comprising: reading, at a first voltage level, first data from a first portion of the plurality of first memory cells; performing an error checking and correction (ECC) operation on the first data to generate ECC-performed first data; reading, at a second voltage level, second data that is read from the first portion of the plurality of first memory cells when a number of error bits of the ECC-performed first data exceeds a threshold correctable by the ECC operation; performing the ECC operation on the second data to generate ECC-performed second data; outputting to the nonvolatile memory device first page data that includes either the ECC-performed first data or the ECC-performed second data; programming the first page data in a first portion of the plurality of second memory cells; reading the programmed first page data in the first portion of the plurality of second memory cells at a first time; programming in a second portion of the plurality of first memory cells the programmed first page data that is read at the first time; reading the programmed first page data in the first portion of the plurality of second memory cells at a second time; and re-programming in the second portion of the plurality of first memory cells the programmed first page data that is read at the second time. ### Claim 20 (depends on 19) The method of claim 19, wherein the programming in the second portion of the plurality of first memory cells the first page data is performed, without the ECC operation on the first page data. ### Claim 21 (depends on 19) The method of claim 19, further comprising performing the ECC operation on third data that is read from a third portion of the plurality of first memory cells, the third data being included in second page data that is output to the nonvolatile memory device from the controller, and the first page data and the second page data are output to the nonvolatile memory device from the controller within a predetermined time period. ### Claim 22 (depends on 21) The method of claim 21, wherein the first page data and the second page data are output to the nonvolatile memory device from the controller after the controller processes a request by an external device. ### Claim 23 (depends on 19) The method of claim 19, wherein the nonvolatile memory device includes a memory cell array having a vertical or stack-type three-dimensional array structure. ### Claim 24 A memory system comprising: a nonvolatile memory device including a plurality of first memory cells and a plurality of second memory cells, each of the plurality of first memory cells being configured to store 3-bit data, each of the plurality of second memory cells being configured to store 1-bit data, the nonvolatile memory device including a memory cell array having a vertical or stack-type three-dimensional array structure; and a controller configured to control the nonvolatile memory device to perform a read operation, a program operation and a re-program operation, wherein the controller is configured to perform an error checking and correction (ECC) operation on first data to generate ECC-performed first data, the first data being read from a first portion of the plurality of first memory cells at a first voltage level, the controller is configured to perform a read retry operation and the ECC operation on second data to generate ECC-performed second data when a number of error bits of the ECC-performed first data exceeds a threshold correctable by the ECC operation, the read retry operation including reading the second data stored in the first portion of the plurality of first memory cells at a second voltage level that is different from the first voltage level, the second data being read from the first portion of the plurality of first memory cells, the controller is configured to output to the nonvolatile memory device first page data including either the ECC-performed first data or the ECC-performed second data, the nonvolatile memory device is configured to program the first page data in a first portion of the plurality of second memory cells, the nonvolatile memory device is configured to read the programmed first page data in the first portion of the plurality of second memory cells, the nonvolatile memory device is configured to program in a second portion of the plurality of first memory cells the programmed first page data that is read at a first time from the first portion of the plurality of second memory cells, the nonvolatile memory device is configured to re-program in the second portion of the plurality of first memory cells the programmed first page data that is read at a second time from the first portion of the plurality of second memory cells, wherein the first time is different from the second time. ### Claim 25 (depends on 24) The memory system of claim 24, wherein the controller is configured to program in the second portion of the plurality of first memory cells the first page data that is read at the first time from the first portion of the plurality of second memory cells, without performing the ECC operation on the first page data. ### Claim 26 (depends on 24) The memory system of claim 24, wherein the controller is configured to perform the read retry operation and the ECC operation on third data that is read from the first portion of the plurality of first memory cells. ### Claim 27 (depends on 24) The memory system of claim 24, wherein the controller is configured to perform the ECC operation on fourth data that is read from the second portion of the plurality of first memory cells. ### Claim 28 (depends on 27) The memory system of claim 27, wherein the first portion of the plurality of first memory cells and the second portion of the plurality of first memory cells are included in the same memory block. ### Claim 29 (depends on 27) The memory system of claim 27, wherein the fourth data is included in second page data that is output to the nonvolatile memory device from the controller. ### Claim 30 (depends on 28) The memory system of claim 28, wherein each of the first page data and the second page data is valid page data.