# US 2016/0259684 A1 · Memory device, memory system and method of operating the same

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- Number: US 2016/0259684 A1
- Document ID: US20160259684A1
- Status: Published application
- Kind: A1
- Application number: 15/154,277
- Filed: 2016-05-13
- Published: 2016-09-08
- Earliest claimed: 2012-04-12
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: JONG-WOOK PARK
- Web page: https://patentgrep.com/patent/US20160259684A1

## CPC

- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- H03M 13/05: using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits {(H03M13/2906 takes precedence)}
- H03M 13/09: Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A memory device, a memory system, and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells and a write command determination unit (WCDU) that determines whether a write command input to the memory device is (to be) accompanied a masking signal. The WCDU produces a first control signal if the input write command is (to be) accompanied by a masking signal. A data masking unit combines a portion of read data read from the memory cell array with a corresponding portion of input write data corresponding to the write command and generates modulation data in response to the first control signal. An error correction code (ECC) engine generates parity of the modulation data.

## Claims

### Claim at position 1

1-35. (canceled)

### Claim 36

A synchronous dynamic random access memory (DRAM) device comprising:
a memory cell array including a plurality of memory cells;
a parity region including a plurality of memory cells;
a clock pin receiving a clock signal;
a plurality of data pins receiving write data;
a plurality of command/address pins receiving command/address signals comprising a write command and a write address, wherein the write address indicates a location of the memory cell array for the write data to be written into;
a data masking pin receiving a data masking signal, wherein the data masking signal indicates a first portion of the write data to be masked, wherein the first portion of the write data is addressed by the write address to be written into a first portion of the memory cell array;
a write command determination unit configured to determine whether the write command is a normal write command or a read modify write command, and to produce a first control signal if the write command is the read modify write command;
a data modulation unit configured to generate modulation data in response to the first control signal by reading the first portion of memory cell array to produce a first read data and replacing the first portion of write data with the first read data, wherein the size of the modulation data is equal to the size of the write data;
an error correction code (ECC) engine configured to generate a parity of the modulation data if the write command is the read modify write command; and
a writing unit configured to write at least a second portion of the write data and the parity of the modulation data into the memory cell array and the parity region respectively if the write command is the read modify write command, wherein the second portion of the write data is a portion of write data excepting the first portion of the write data.

### Claim 37 (depends on 36)

The memory device of claim 36, wherein the writing unit is further configured to write back the first read data into the first portion of the memory cell array.

### Claim 38 (depends on 36)

The memory device of claim 36, wherein the data masking signal is inputted in synchronization with the first portion of the write data.

### Claim 39 (depends on 36)

The memory device of claim 36, wherein the error correction code (ECC) engine is further configured to generate a parity of the write data if the write command is the normal write command.

### Claim 40 (depends on 36)

The memory device of claim 36, wherein the writing unit is further configured to write the write data and the parity of the write data into the memory cell array and the parity region respectively if the write command is the normal write command.

### Claim 41 (depends on 36)

The memory device of claim 36, wherein the normal write command and the read modify write command are distinguished each other by at least one of the command/address signals.

### Claim 42 (depends on 41)

The memory device of claim 41, wherein the normal write command and the read modify write command are distinguished each other by keeping at least one of the command/address signals with a logic level low at a rising edge of the clock signal of the write command for the normal write command and with a logic level high at a rising edge of the clock signal of the write command for the read modify write command respectively.

### Claim 43 (depends on 36)

The memory device of claim 36, wherein the modulation data has a bit-size corresponding to the smallest encoding unit of the ECC engine.

### Claim 44 (depends on 36)

The memory device of claim 36, wherein the memory device, if the write command is the read modify command, is configured to enable a first column select signal for reading the first portion of the memory cell array and thereafter to enable a second column select signal for writing at least the second portion of write data into the memory cell array.

### Claim 45 (depends on 44)

The memory device of claim 44, wherein the memory device, if the write command is the read modify write command, is configured to enable a first column select signal for reading the first portion of the memory cell array before receiving the data masking signal.

### Claim 46 (depends on 44)

The memory device of claim 44, wherein the memory device, if the write command is the read modify command, is further configured to enable a third column select signal for writing the parity of the modulation data into the parity region.

### Claim 47 (depends on 36)

The memory device of claim 36, wherein the memory device, if the write command is the normal command, is configured to enable both a first column select signal and a second column select signal for writing the write data.

### Claim 48 (depends on 47)

The memory device of claim 47, wherein the memory device, if the write command is the normal command, is further configured to enable a third column select signal for writing the parity of the write data into the parity region.

### Claim 49

A method of writing data in a synchronous dynamic random access (SDRAM) memory device including an error correction code (ECC) engine, the method comprising:
receiving command/address signals comprising a write command, a write address and write data, wherein the write data is written into a memory cell array of the memory device based on the write command and the write address;
receiving a data masking signal indicating a first portion of the write data to be masked, wherein the first portion of the write data is addressed by the write address to be written into a first portion of the memory cell array;
determining whether the write command is a read modify write command or a normal write command based on at least one of the command/address signals;
reading the first portion of the memory cell array to produce a first read data if the write command is the read modify write command;
generating modulation data by replacing the first portion of the write data with the first read data, wherein the size of the modulation data is equal to the size of the write data;
encoding a parity of the modulation data by using the ECC engine; and
writing at least a second portion of the write data and the parity of the modulation data into the memory cell array and a parity region respectively if the write command is the read modify write command, wherein the second portion of the write data is a portion of write data excepting the first portion of the write data

### Claim 50 (depends on 49)

The method of claim 49, wherein the method further includes writing back the first read data into the first portion of the memory cell array.

### Claim 51 (depends on 49)

The method of claim 49, wherein the data masking signal is inputted in synchronization with the first portion of the write data.

### Claim 52 (depends on 49)

The method of claim 49, wherein the method further generating a parity of the write data if the write command is the normal write command.

### Claim 53 (depends on 49)

The method of claim 49, wherein the method further writing the write data and the parity of the write data into the memory cell array and the parity region respectively if the write command is the normal write command.

### Claim 54 (depends on 49)

The method of claim 49, wherein the modulation data has a bit-size corresponding to the smallest encoding unit of the ECC engine.

### Claim 55 (depends on 49)

The method of claim 49, wherein executing the read modify write command comprises enabling a first column select signal for reading the first portion of memory cells and thereafter enabling a second column select signal for writing the second portion of write data into the memory cells.

### Claim 56 (depends on 55)

The memory device of claim 55, wherein enabling a first column select signal for reading the first portion of the memory cell array before receiving the data masking signal.

### Claim 57 (depends on 55)

The method of claim 55, wherein writing the parity of the modulation data into the parity region comprises enabling a third column select signal.

### Claim 58 (depends on 49)

The method of claim 49, wherein the method further includes executing the normal command by enabling both a first column select signal and a second column select signal for writing the write data.