# US 2016/0259683 A1 · Memory controller, memory system and memory control method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2016/0259683 A1 - Document ID: US20160259683A1 - Status: Published application - Kind: A1 - Application number: 14/790,331 - Filed: 2015-07-02 - Published: 2016-09-08 - Earliest claimed: 2015-03-04 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kabushiki Kaisha Toshiba - Inventors: Kenji SAKURADA - Web page: https://patentgrep.com/patent/US20160259683A1 ## CPC - H03M 13/45: Soft decoding, i.e. using symbol reliability information (H03M13/41 takes precedence) - G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 29/021: {in voltage or current generators} - G11C 29/028: {with adaption or trimming of parameters} - H03M 13/3723: {using means or methods for the initialisation of the decoder} - H03M 13/6325: {Error control coding in combination with demodulation} - G11C 7/14: Dummy cell management; Sense reference voltage generators - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract According to the embodiment, a memory controller includes a memory interface which performs a first reading using a read voltage including a hard decision voltage and a second reading using a plurality of read voltages within a predetermined voltage range, a shift value calculation unit which calculates an update value of the hard decision voltage based on the reading result by the second reading, a storage unit which stores the update value, a decoding unit which performs decoding based on likelihood information according to the reading result, and a controller which makes the memory controller perform the first reading, makes the decoding unit perform the decoding by using the likelihood information using a reading result by the second reading when the decoding has been failed, and makes the memory controller perform the first reading by using the update value when the corresponding update value is stored in the storage unit. ## Claims ### Claim 1 A memory system comprising: a non-volatile memory configured to store a code word; a memory interface configured to control reading/writing data from/into the non-volatile memory and perform a first reading and second reading, the first reading being reading the code word from the non-volatile memory by using a read voltage including a hard decision voltage which is a voltage used to make a hard decision of the code word stored in the non-volatile memory, the second reading being reading the code word from the non-volatile memory using a plurality of read voltages within a predetermined voltage range; a conversion unit configured to convert a reading result by the first reading into first likelihood information and convert a reading result by the second reading into second likelihood information; a decoding unit configured to perform decoding based on the first likelihood information or the second likelihood information; and a controller configured to make the memory interface perform the first reading, make the decoding unit perform the decoding based on the first likelihood information, and make the memory interface perform the second reading and make the decoding unit perform the decoding based on the second likelihood information in a case where the decoding based on the first likelihood information has been failed. ### Claim 2 (depends on 1) The memory system according to claim 1, comprising: a calculation unit configured to calculate an update value of the hard decision voltage based on the reading result by the second reading of the plurality of memory cells of the non-volatile memory; and a storage unit configured to store the update value for each of the plurality of memories, wherein the controller makes the memory interface use the update value stored in the storage unit as the hard decision voltage in the first reading. ### Claim 3 (depends on 2) The memory system according to claim 2, wherein the calculation unit calculates the update value for each of the plurality of memory cells corresponding to a block which is a data erasing unit in the non-volatile memory. ### Claim 4 (depends on 1) The memory system according to claim 1, wherein the first reading includes a reading performed by using the hard decision voltage, a reading performed by using a first read voltage lower than the hard decision voltage, and a reading performed by using a second read voltage higher than the hard decision voltage. ### Claim 5 (depends on 1) The memory system according to claim 1, wherein the non-volatile memory includes a memory cell having a storage capacity of N bits in accordance with 2 to the power of N threshold voltage distributions, where N is a natural number that is greater than 1, and the predetermined voltage range includes voltage regions, each of the voltage regions corresponding to each of threshold voltage distributions except a smallest threshold voltage distribution among the threshold voltage distributions. ### Claim 6 (depends on 1) The memory system according to claim 1, comprising: a counter configured to select one read voltage from among the plurality of read voltages based on the reading result by the second reading, wherein the non-volatile memory includes a plurality of memory cells, each of the plurality of memory cells having a storage capacity of one bit or more, the second reading outputs a plurality of read data items for each memory cell as the reading result by the second reading, each of the plurality of read data items corresponding to each of the plurality of read voltages, and the conversion unit obtains the second likelihood information based on the selected read voltage. ### Claim 7 (depends on 6) The memory system according to claim 6, wherein the counter checks the plurality of read data items in ascending order of the plurality of read voltages, and selects a third read voltage as the selected read voltage when a first read data item of the plurality of read data items is different from a second read data item of the plurality of read data items, the third read voltage corresponding to the first read data item, the third read voltage being larger than a fourth read voltage corresponding to the second read data item. ### Claim 8 (depends on 7) The memory system according to claim 7, wherein the memory cell has a storage capacity of two or more bits, and the conversion unit obtains the second likelihood information based on a first likelihood information table corresponding to a first bit and including values respectively corresponding to the plurality of read voltages when the read data corresponds to the first bit of two or more bits and obtains the second likelihood information based on a second likelihood information table corresponding to a second bit and including values respectively corresponding to the plurality of read voltages when the read data corresponds to the second bit of two or more bits. ### Claim 9 (depends on 8) The memory system according to claim 8, wherein the counter indicates the selected read voltage as a numerical value according to the read voltage value. ### Claim 10 (depends on 1) The memory system according to claim 1, wherein the code word is a code word based on a LDPC. ### Claim 11 A method for controlling a non-volatile memory for storing a code word, the method comprising: performing a first reading to read the code word from the non-volatile memory by using a read voltage including a hard decision voltage which is used to make a hard decision of the code word stored in the non-volatile memory; converting a reading result by the first reading into first likelihood information; performing decoding based on the first likelihood information; and performing a second reading by using a plurality of read voltages within a predetermined voltage range, converting a reading result by the second reading into second likelihood information, and performing decoding based on the second likelihood information when the decoding based on the first likelihood information has been failed. ### Claim 12 (depends on 11) The method according to claim 11, further comprising: calculating an update value of the hard decision voltage; and storing the update value in a storage unit based on the reading result by the second reading, wherein the update value stored in the storage unit is used as the hard decision voltage in the first reading. ### Claim 13 (depends on 12) The method according to claim 12, further comprising: calculating the update value for each of a plurality of memory cells corresponding to a block which is a data erasing unit in the non-volatile memory. ### Claim 14 (depends on 11) The method according to claim 11, wherein the first reading includes reading by using the hard decision voltage, a reading by using a first read voltage lower than the hard decision voltage, and a reading by using a second read voltage higher than the hard decision voltage. ### Claim 15 (depends on 11) The method according to claim 11, wherein the non-volatile memory includes a memory cell having a storage capacity of N bits in accordance with 2 to the power of N threshold voltage distributions, where N is a natural number that is greater than 1, and the predetermined voltage value includes voltage regions, each of the voltage regions corresponding to each of threshold voltage distributions except a smallest threshold voltage distribution among the threshold voltage distributions. ### Claim 16 (depends on 11) The method according to claim 11, wherein the non-volatile memory includes a plurality of memory cells, each of the plurality of memory cells having a storage capacity of one bit or more, the second reading includes outputting a plurality of read data items for each memory cell as the reading result by the second reading, each of the plurality of read data items corresponding to each of the plurality of read voltages, and the converting into the second likelihood information includes selecting one read voltage from among the plurality of read voltages based on the reading result by the second reading and obtaining the second likelihood information based on the selected read voltage. ### Claim 17 (depends on 16) A memory control method according to claim 16, wherein the converting into the second likelihood information comprises: checking the plurality of read data items in ascending order of the plurality of read voltages; and selecting a third read voltage as the selected read voltage when a first read data item of the plurality of read data items is different from a second read data item of the plurality of read data items, the third read voltage corresponding to the first read data item, the third read voltage being larger than a fourth read voltage corresponding to the second read data item. ### Claim 18 (depends on 17) The method according to claim 17, wherein the memory cell have a storage capacity of two or more bits, and the method further comprises: obtaining the second likelihood information based on a first likelihood information table corresponding to a first bit and including values respectively corresponding to the plurality of read voltages when the read data corresponds to the first bit of two or more bits; and obtaining the second likelihood information based on a second likelihood information table corresponding to a second bit and including values respectively corresponding to the plurality of read voltages when the read data corresponds to the second bit of two or more bits. ### Claim 19 (depends on 18) The method according to claim 18, wherein the conversion into the second likelihood information indicates the selected read voltage as a numerical value according to the read voltage value. ### Claim 20 (depends on 11) The method according to claim 11, wherein the code word is a code word based on a LDPC.