# US 2016/0259646 A1 · Elapsed Cycle Timer in Last Branch Records

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- Number: US 2016/0259646 A1
- Document ID: US20160259646A1
- Status: Published application
- Kind: A1
- Application number: 15/155,204
- Filed: 2016-05-16
- Published: 2016-09-08
- Earliest claimed: 2013-06-20
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Ahmad Yasin; Michael W. Chynoweth; Ofer Levy; Jason W. Brandt; Angela Schmid
- Web page: https://patentgrep.com/patent/US20160259646A1

## CPC

- G06F 9/3806: {using address prediction, e.g. return stack, branch history buffer}
- G06F 9/30098: {Register arrangements}
- G06F 9/323: {for indirect branch instructions}
- G06F 11/3419: {by assessing time}
- G06F 11/348: {Circuit details, i.e. tracer hardware}
- G06F 2201/865: Monitoring of software
- G06F 2201/88: Monitoring involving counting
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device. The processing device further includes at least one register communicably coupled to the LBR counter, the at least one register to provide an LBR structure comprising a plurality of LBR entries. An LBR entry of the plurality of LBR entries includes an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter in response to creation of the LBR entry.

## Claims

### Claim 1

A processing device, comprising:
a last branch record (LBR) counter to iterate with each cycle of the processing device; and
at least one register communicably coupled to the LBR counter, the at least one register to provide an LBR structure comprising a plurality of LBR entries, wherein an LBR entry of the plurality of LBR entries comprises:
an address instruction pointer (IP) of a branch instruction executed by the processing device;
an address IP of a target of the branch instruction; and
an elapsed time field that stores a value of the LBR counter in response to creation of the LBR entry.

### Claim 2 (depends on 1)

The processing device of claim 1, wherein the LBR counter resets upon creation of each LBR entry.

### Claim 3 (depends on 1)

The processing device of claim 1, wherein the value of the LBR counter comprises a number of cycles of the processing device since addition of an immediately-previous LBR entry to the LBR entry, wherein the cycles comprise at least one of core clock cycles of the processing device or reference clock cycles of the processing device.

### Claim 4 (depends on 1)

The processing device of claim 1, wherein the LBR structure is an array data structure.

### Claim 5 (depends on 1)

The processing device of claim 1, wherein the elapsed time field is part of a last branch information portion of the LBR entry.

### Claim 6 (depends on 1)

The processing device of claim 1, wherein the at least one register is a model-specific register (MSR).

### Claim 7 (depends on 1)

The processing device of claim 1, wherein the address IP of the branch instruction and the address IP of the target of the branch instruction are obtained from address IP calculation components of the processing device.

### Claim 8 (depends on 1)

The processing device of claim 1, wherein the LBR counter is to increment at intervals of cycles to decrease a resolution of the LBR counter and increase a saturation threshold of the LBR counter.

### Claim 9

A method, comprising:
recording, by a processing device in an entry of a last branch record (LBR) structure of the processing device, an address instruction pointer (IP) of a branch instruction executed by the processing device, wherein the LBR structure is implemented in at least one register of the processing device;
recording, in the entry of the LBR structure, an address IP of a target of the branch instruction;
sampling a value of a LBR counter;
recording the value of the LBR counter in an elapsed time field of the entry of the LBR structure; and
resetting the LBR counter.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
receiving a signal indicating that the branch instruction is to be recorded in the LBR structure; and
accessing the entry in the LBR structure to perform the recording the address IPs and the recoding the value of the LBR counter.

### Claim 11 (depends on 9)

The method of claim 9, wherein the LBR structure comprises a plurality of LBR entries and wherein the LBR counter resets upon creation of each LBR entry in the LBR structure.

### Claim 12 (depends on 9)

The method of claim 9, wherein the value of the LBR counter comprises a number of cycles of the processing device since addition of an immediately-previous LBR entry to the LBR entry, wherein the cycles comprise at least one of core clock cycles of the processing device or reference clock cycles of the processing device.

### Claim 13 (depends on 9)

The method of claim 9, wherein the elapsed time field is part of a last branch information portion of the LBR entry.

### Claim 14 (depends on 9)

The method of claim 9, wherein the LBR counter is to increment at intervals of cycles to decrease a resolution of the LBR counter and increase a saturation threshold of the LBR counter.

### Claim 15

An system comprising:
a memory to store a branch instruction; and
a processing device communicably coupled to the memory, the processing device comprising:
an execution unit to execute the branch instruction;
a last branch record (LBR) counter to iterate with each cycle of the execution unit; and
at least one register communicably coupled to the LBR counter, the at least one register to, responsive to execution of the branch instruction by the execution unit:
store, in an LBR entry of an LBR structure provided by the at least one register, an address instruction pointer (IP) of the branch instruction;
store, in the LBR entry, an address IP of a target of the branch instruction; and
store, in an elapsed time filed of the LBR entry, a value sampled from the LBR counter upon creation of the LBR entry.

### Claim 16 (depends on 15)

The system of claim 15, wherein the processing device is further to:
send a signal to the LBR structure and the LBR counter indicating that the branch instruction is to be recorded in the LBR structure; and
access the entry in the LBR structure to perform the recording the address IPs and the recoding the value.

### Claim 17 (depends on 15)

The system of claim 15, wherein the LBR structure comprises a plurality of LBR entries and wherein the LBR counter resets upon creation of each LBR entry in the LBR structure.

### Claim 18 (depends on 15)

The system of claim 15, wherein the value of the LBR counter comprises a number of cycles of the processing device since addition of an immediately-previous LBR entry to the LBR entry, wherein the cycles comprise at least one of core clock cycles of the processing device or reference clock cycles of the processing device.

### Claim 19 (depends on 15)

The system of claim 15, wherein the at least one register is a model-specific register (MSR).

### Claim 20 (depends on 15)

The system of claim 15, wherein the address IP of the branch instruction and the address IP of the target of the branch instruction are obtained from address IP calculation components of the processing device.

### Claim 21 (depends on 15)

The system of claim 15, wherein the LBR counter is to increment at intervals of cycles to decrease a resolution of the LBR counter and to increase a saturation threshold of the LBR counter.