# US 2016/0259398 A1 · Systems and methods for implementing power collapse in a memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2016/0259398 A1 - Document ID: US20160259398A1 - Status: Published application - Kind: A1 - Application number: 14/638,185 - Filed: 2015-03-04 - Published: 2016-09-08 - Earliest claimed: 2015-03-04 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Adam Edward NEWHAM; Kenneth David EASTON; Rashid Ahmed Akbar ATTAR - Web page: https://patentgrep.com/patent/US20160259398A1 ## CPC - G06F 1/32: Means for saving power - G06F 1/3287: by switching off individual functional units in the computer system - G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode - G06F 1/3246: by software initiated power-off - G06F 1/3275: {Power saving in memory, e.g. RAM, cache} - G06F 1/3293: by switching to a less power-consuming processor, e.g. sub-CPU - G06F 12/0246: {in block erasable memory, e.g. flash memory} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A power management system for stack memory thread tasks according to some examples of the disclosure may include a non-collapsible memory region, a collapsible memory region configured below the non-collapsible memory region, a memory management unit in communication with the non-collapsible memory region and the collapsible memory region, the memory management unit operable to allocate a portion of the non-collapsible memory region and a portion of the collapsible memory region to a thread task upon initialization of the thread task and power down the portion of the collapsible memory region allocated to the thread task upon receiving a power down command. ## Claims ### Claim 1 A power management system for thread tasks, comprising: a non-collapsible memory region; a collapsible memory region; a memory management unit in communication with the non-collapsible memory region and the collapsible memory region, the memory management unit operable to allocate a portion of the non-collapsible memory region and a portion of the collapsible memory region to a thread task upon initialization of the thread task, and wherein the memory management unit is operable to power down the portion of the collapsible memory region allocated to the thread task upon receiving a power down command. ### Claim 2 (depends on 1) The system of claim 1, further comprising a polling entity in communication with the memory management unit, the polling entity operable to poll the thread task to determine if the thread task is complete. ### Claim 3 (depends on 2) The system of claim 2, wherein the polling entity sends the power down command to the memory management unit when the thread task is complete. ### Claim 4 (depends on 3) The system of claim 3, wherein the polling entity sends the power down command to the memory management unit when all thread tasks associated with the collapsible memory region are complete. ### Claim 5 (depends on 1) The system of claim 1, wherein the non-collapsible memory region is a read write accessible non-volatile memory and the collapsible memory region is a read write accessible volatile memory. ### Claim 6 (depends on 5) The system of claim 5, further comprising copying the non-collapsible memory region to the collapsible memory region for access and wherein the power down comprises performing a copy from the collapsible memory region to the non-collapsible memory region. ### Claim 7 (depends on 1) The system of claim 1, wherein the power down comprises compressing the collapsible memory region allocated to the thread task. ### Claim 8 (depends on 1) The system of claim 1, further comprising a switch in communication with the memory management unit, the switch being operable to switch off a power signal or a clock signal to the collapsible memory region upon receiving a power down command from the memory management unit. ### Claim 9 (depends on 1) The system of claim 1, wherein the non-collapsible memory region, the collapsible memory region, and the memory management unit are incorporated into a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, and further including the device. ### Claim 10 (depends on 1) The system of claim 1, further comprising an interrupt entity in communication with the memory management unit, the interrupt entity operable to query the thread task to determine if the thread task is complete. ### Claim 11 (depends on 10) The system of claim 10, wherein the interrupt entity sends the power down command to the memory management unit when the thread task is complete. ### Claim 12 (depends on 11) The system of claim 11, wherein the interrupt entity sends the power down command to the memory management unit when all thread tasks associated with the collapsible memory region are complete. ### Claim 13 A method of powering down a memory, comprising: partitioning a memory into a first region and a second region, the second region being a stack memory with associated thread tasks; receiving a power down command; and upon receiving a power down command, maintaining power to the first region and polling each associated thread task to determine if the second region associated with the thread task should be powered down or maintained. ### Claim 14 (depends on 13) The method of claim 13, wherein each stack memory includes a non-volatile portion and volatile region and wherein the non-volatile region remains active and the volatile region is powered down. ### Claim 15 (depends on 14) The method of claim 14, wherein data in the powered down region is compressed instead of completely powered down. ### Claim 16 (depends on 13) The method of claim 13, wherein powering down the second region includes sending a power down command to a switch that powers the second region to open the switch. ### Claim 17 (depends on 13) The method of claim 13, wherein powering down the second region includes sending a power down command to a switch that inputs a clock signal to the second region to open the switch. ### Claim 18 A non-transitory computer-readable memory to store instructions that when executed on a system cause the system to perform a process, the process comprising: partitioning a memory into a first region and a second region, the second region being a stack memory with associated thread tasks; receiving a power down command; and upon receiving a power down command, maintaining power to the first region and polling each associated thread task to determine if the second region associated with the associated thread task should be powered down or maintained. ### Claim 19 (depends on 18) The non-transitory computer-readable memory of claim 18, wherein each stack memory includes a non-volatile portion and volatile region and wherein the non-volatile region remains active and the volatile region is powered down. ### Claim 20 (depends on 19) The non-transitory computer-readable memory of claim 19, wherein data in the powered down region is compressed instead of completely powered down.