# US 2016/0259385 A1 · Impedance adjustment > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2016/0259385 A1 - Document ID: US20160259385A1 - Status: Published application - Kind: A1 - Application number: 14/639,375 - Filed: 2015-03-05 - Published: 2016-09-08 - Earliest claimed: 2015-03-05 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Qiang Tang - Web page: https://patentgrep.com/patent/US20160259385A1 ## CPC - G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} - G06F 13/4072: {Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002)} - G06F 13/4086: {Bus impedance matching, e.g. termination} - H03K 19/0005: {Modifications of input or output impedance} - H03K 19/017545: {Coupling arrangements; Impedance matching circuits} - H03K 19/018557: {Coupling arrangements; Impedance matching circuits} - H03H 11/28: Impedance matching networks - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) ## Abstract Integrated circuit devices and methods of operating integrated circuit devices are useful in impedance adjustment. Integrated circuit devices include a signal driver circuit having an output node, a voltage node, and a first termination device and a second termination device connected in parallel between the voltage node and the output node. The first termination device and the second termination device each have a particular configuration of switchable resistances, and different strengths. Methods include connecting a node of the integrated circuit device to a first voltage node through a reference resistance, connecting the node to a second voltage node through a termination device, adjusting a resistance value of the termination device and comparing a resulting voltage level to a reference voltage. The reference voltage has a voltage level different than half-way between a voltage level of the first voltage node and a voltage level of the second voltage node. ## Claims ### Claim 1 An integrated circuit device, comprising: a controller; and a signal driver circuit comprising: an output node; a voltage node; a first termination device and a second termination device connected in parallel between the voltage node and the output node; wherein the first termination device and the second termination device are each connected to a respective set of signal lines, each set of signal lines having a same number of signal lines; wherein the first termination device and the second termination device each have a particular configuration of switchable resistances; and wherein the first termination device has a different strength than the second termination device; and wherein each switchable resistance of the particular configuration of switchable resistances comprises a switch and a resistance connected in series; wherein at least one switchable resistance of the particular configuration of switchable resistances comprises a plurality of switches connected in parallel with each other and each connected in series with a resistance; and wherein the controller is adapted to apply a same set of control signals to the configuration of switchable resistances of the first termination device through its set of signal lines and to the configuration of switchable resistances of the second termination device through its set of signal lines when activating both the first termination device and the second termination device. ### Claim at position 2 2-3. (canceled) ### Claim 4 (depends on 1) The integrated circuit device of claim 1, wherein each switch comprises a transistor, and wherein each resistance comprises a resistor. ### Claim 5 (depends on 1) The integrated circuit device of claim 1, wherein the particular configuration of switchable resistances comprises a plurality of transistors and a plurality of resistances. ### Claim 6 (depends on 5) The integrated circuit device of claim 5, wherein channel widths of the transistors of the particular configuration of switchable resistances of the second termination device are each a particular fraction of channel widths of their corresponding transistors of the particular configuration of switchable resistances of the first termination device. ### Claim 7 (depends on 6) The integrated circuit device of claim 6, wherein resistance values of the resistances of the particular configuration of switchable resistances of the second termination device are each a particular multiple of resistance values of their corresponding resistances of the particular configuration of switchable resistances of the first termination device. ### Claim 8 (depends on 7) The integrated circuit device of claim 7, wherein the particular multiple is an inverse of the particular fraction. ### Claim 9 (depends on 1) The integrated circuit device of claim 1, wherein the signal driver circuit further comprises: a third termination device connected in parallel with the first termination device and the second termination device between the voltage node and the output node; wherein the first termination device, the second termination device and the third termination device each have the particular configuration of switchable resistances; and wherein the third termination device has a different strength than the first termination device. ### Claim 10 (depends on 9) The integrated circuit device of claim 9, further comprising: wherein channel widths of transistors of the particular configuration of switchable resistances of the second termination device are each a particular fraction of channel widths of their corresponding transistors of the particular configuration of switchable resistances of the first termination device; wherein resistance values of resistances of the particular configuration of switchable resistances of the second termination device are each a particular multiple of resistance values of their corresponding resistances of the particular configuration of switchable resistances of the first termination device; and wherein the particular multiple is an inverse of the particular fraction. ### Claim 11 (depends on 10) The integrated circuit device of claim 10, wherein the strength of the third termination device is the same as the strength of the second termination device. ### Claim 12 (depends on 10) The integrated circuit device of claim 10, wherein the strength of the third termination device is different than the strength of the second termination device. ### Claim 13 (depends on 12) The integrated circuit device of claim 12, wherein the strength of the third termination device is a multiple of the strength of the second termination device. ### Claim 14 (depends on 13) The integrated circuit device of claim 13, wherein the strength of the third termination device plus the strength of the second termination device equals the strength of the first termination device. ### Claim 15 (depends on 13) The integrated circuit device of claim 13, wherein the strength of the third termination device plus the strength of the second termination device is less than the strength of the first termination device. ### Claim 16 (depends on 9) The integrated circuit device of claim 9, further comprising: wherein channel widths of the transistors of the particular configuration of switchable resistances of the second termination device are each a first fraction of channel widths of their corresponding transistors of the particular configuration of switchable resistances of the first termination device; wherein channel widths of the transistors of the particular configuration of switchable resistances of the third termination device are each a second fraction of the channel widths of their corresponding transistors of the particular configuration of switchable resistances of the first termination device; wherein resistance values of the resistances of the particular configuration of switchable resistances of the second termination device are each a first multiple of resistance values of their corresponding resistances of the particular configuration of switchable resistances of the first termination device; wherein resistance values of the resistances of the particular configuration of switchable resistances of the third termination device are each a second multiple of the resistance values of their corresponding resistances of the particular configuration of switchable resistances of the first termination device; wherein the first multiple is an inverse of the first fraction; wherein the second multiple is an inverse of the second fraction; and wherein the second fraction is a multiple of the first fraction. ### Claim 17 An integrated circuit device, comprising: a controller; and a signal driver circuit comprising: a plurality of first termination devices, each having a particular configuration of switchable resistances, and having a first strength; and a plurality of second termination devices, each having the particular configuration of switchable resistances, and each having a strength less than the first strength; wherein each first termination device of the plurality of first termination devices and each second termination device of the plurality of second termination devices are each connected to a respective set of signal lines, each set of signal lines having a same number of signal lines; and wherein the controller is adapted to apply a same set of control signals to the configuration of switchable resistances of each activated first termination device through its respective set of signal lines and to the configuration of switchable resistances of each activated second termination device through its respective set of signal lines. ### Claim 18 (depends on 17) The integrated circuit device of claim 17, wherein the particular configuration of switchable resistances comprises a plurality of transistors and a plurality of resistances, and wherein at least one resistance of the plurality of resistances is connected in series with at least one of the transistors of the plurality of transistors. ### Claim 19 (depends on 18) The integrated circuit device of claim 18, wherein channel widths of each transistor of the particular configuration of switchable resistances of each of the second termination devices are each a particular fraction of channel widths of their corresponding transistors of the particular configuration of switchable resistances of each of the first termination devices, wherein resistance values of the resistances of the particular configuration of switchable resistances of each of the second termination devices are each a particular multiple of resistance values of their corresponding resistances of the particular configuration of switchable resistances of each of the first termination devices, and wherein the particular multiple is an inverse of the particular fraction. ### Claim 20 (depends on 19) The integrated circuit device of claim 19, wherein a number of second termination devices of the plurality of second termination devices is equal to the particular multiple. ### Claim 21 A method of operating an integrated circuit device, comprising: connecting a node of the integrated circuit device to a first voltage node through a reference resistance and connecting the node to a second voltage node through a termination device of a signal driver circuit; adjusting a resistance value of the termination device; comparing a voltage level at the node to a reference voltage, wherein the reference voltage has a voltage level different than half-way between a voltage level of the first voltage node and a voltage level of the second voltage node; when the comparing of the voltage level at the node to the reference voltage is deemed a match of the voltage level at the node and the reference voltage, storing settings of the termination device in response to deeming the match of the voltage level at the node and the reference voltage; and when the comparing of the voltage level at the node to the reference voltage is not deemed a match of the voltage level at the node and the reference voltage, further adjusting the resistance value of the termination device. ### Claim 22 (depends on 21) The method of claim 21, wherein comparing a voltage level at the node to a reference voltage comprises the reference voltage having a voltage level that is less than half-way between the voltage level of the first voltage node and the voltage level of the second voltage node. ### Claim 23 (depends on 21) The method of claim 21, wherein adjusting a resistance value of the termination device comprises incrementally adjusting the resistance value of the termination device. ### Claim 24 (depends on 23) The method of claim 23, wherein incrementally adjusting the resistance value of the termination device comprises incrementally adjusting the resistance value of the termination device from a lowest adjustable value. ### Claim 25 (depends on 21) The method of claim 21, wherein comparing of the voltage level at the node to the reference voltage comprises applying the voltage level at the node to a first input of a voltage comparator and applying the reference voltage to a second input of the voltage comparator. ### Claim 26 (depends on 25) The method of claim 25, wherein comparing of the voltage level at the node to the reference voltage is deemed a match when a logic value of an output of the voltage comparator transitions. ### Claim 27 (depends on 21) The method of claim 21, wherein storing settings of the termination device in response to deeming the match comprises storing current settings of the termination device when the voltage level at the node and the reference voltage were deemed to match. ### Claim 28 (depends on 21) The method of claim 21, wherein storing settings of the termination device in response to deeming the match comprises storing settings of the termination device used prior to when the voltage level at the node and the reference voltage were deemed to match. ### Claim 29 (depends on 18) The integrated circuit device of claim 18, further comprising: wherein channel widths of each transistor of the particular configuration of switchable resistances of a first portion of the second termination devices are each a first fraction of channel widths of their corresponding transistors of the particular configuration of switchable resistances of each of the first termination devices; wherein channel widths of each transistor of the particular configuration of switchable resistances of a second portion of the second termination devices are each a second fraction of channel widths of their corresponding transistors of the particular configuration of switchable resistances of each of the first termination devices; wherein resistance values of the resistances of the particular configuration of switchable resistances of the first portion of the second termination device are each a first multiple of resistance values of their corresponding resistances of the particular configuration of switchable resistances of each of the first termination devices; wherein resistance values of the resistances of the particular configuration of switchable resistances of the second portion of the second termination device are each a second multiple of resistance values of their corresponding resistances of the particular configuration of switchable resistances of each of the first termination devices; wherein the first multiple is an inverse of the first fraction; wherein the second multiple is an inverse of the second fraction; and wherein the second fraction is a multiple of the first fraction. ### Claim 30 (depends on 29) The integrated circuit device of claim 29, wherein a sum of the first fraction and the second fraction is less than or equal to one.