# US 2016/0259352 A1 · Semiconductor device

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- Number: US 2016/0259352 A1
- Document ID: US20160259352A1
- Status: Published application
- Kind: A1
- Application number: 14/833,712
- Filed: 2015-08-24
- Published: 2016-09-08
- Earliest claimed: 2015-03-04
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Kabushiki Kaisha Toshiba
- Inventors: Toshiyuki KOUCHI
- Web page: https://patentgrep.com/patent/US20160259352A1

## CPC

- G05F 1/46: wherein the variable actually regulated by the final control device is DC (G05F1/625 takes precedence)
- H10W 90/00: Package configurations
- H10W 72/07254: {changes in dispositions}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/9226: {with via interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device of one embodiment includes semiconductor chips. While the semiconductor device is receiving a power supply and a chip enable signal which is negated, all external terminals of the semiconductor chips are at the same logic level.

## Claims

### Claim 1

A semiconductor device comprising:
semiconductor chips, wherein
while the semiconductor device is receiving a power supply and a chip enable signal which is negated, all external terminals of the semiconductor chips are at the same logic level.

### Claim 2 (depends on 1)

The device of claim 1, wherein
a first semiconductor chip of the semiconductor chips comprises:
a first terminal of all the external terminals, and
a latch storing the same logic level as a logic level at the first terminal.

### Claim 3 (depends on 2)

The device of claim 2, wherein
the first semiconductor chip further comprises:
a second terminal of all the external terminals,
a logic circuit which generates a logic level of inversion of the logic level at the first terminal at the second terminal; and
a controller which disables the logic circuit after the latch starts the storing of the same logic level as the logic level at the first terminal.

### Claim 4 (depends on 3)

The device of claim 3, wherein
the same logic level at all the external terminals is a low level.

### Claim 5 (depends on 1)

The device of claim 1, wherein
a first semiconductor chip of the semiconductor chips comprises:
a substrate;
a first terminal of all the external terminals on a first surface of the substrate;
a second terminal of all the external terminals on a side of the first semiconductor chip opposite to the first surface; and
a logic circuit which generates the same logic level as a logic level at the first terminal at the second terminal.

### Claim 6 (depends on 1)

The device of claim 1, wherein
all the external terminals comprise first terminals at a first side of each of the semiconductor chips and second terminals at a second side of each of the semiconductor chips, the second side being opposite to the first side, and
the first terminals of each of a subset of the semiconductor chips excluding two of the semiconductor chips at both ends are coupled to the second terminals of another of the subset of the semiconductor chips on a one-to-one basis.

### Claim 7 (depends on 6)

The device of claim 6, wherein:
each of the semiconductor chips comprises a latch storing the same logic level as a logic level at one of the first terminals of that semiconductor chip.

### Claim 8 (depends on 7)

The device of claim 7, wherein
each of the semiconductor chips further comprises:
a logic circuit which generates a logic level of inversion of the logic level at the one of the first terminals of that semiconductor chip at one of the second terminals of that semiconductor chip; and
a controller which disables the logic circuit of that semiconductor chip after the latch starts the storing of the same logic level as the logic level at the one of the first terminals.

### Claim 9 (depends on 3)

The device of claim 3, wherein
the same logic level at all the external terminals is a low level.

### Claim 10

A semiconductor device comprising:
semiconductor chips, each of which comprises
a first terminal at a first side,
a second terminal at a second side opposite to the first terminal, and
a logic circuit which generates a logic level of inversion of a logic level at the first terminal at the second terminal, wherein
while the semiconductor device is receiving a power supply and a chip enable signal which is negated, the first and second terminals of each of the semiconductor chips are at the same logic level.

### Claim 11 (depends on 10)

The device of claim 10, wherein:
a first semiconductor chip of the semiconductor chips further comprises a latch storing the same logic level as a logic level at the first terminal of the first semiconductor chip.

### Claim 12 (depends on 11)

The device of claim 11, wherein:
the first semiconductor chip further comprises a controller which disables the logic circuit of the first semiconductor chip after the latch starts the storing of the same logic level as the logic level at the first terminal.

### Claim 13 (depends on 12)

The device of claim 12, wherein
the same logic level at the first and second terminals of each of the semiconductor chips is a low level.

### Claim 14 (depends on 10)

The device of claim 10, wherein
a first semiconductor chip of the semiconductor chips comprises:
a substrate;
a third terminal on a first surface of the substrate;
a fourth terminal at a side of the first semiconductor chip opposite to the first surface, and
a logic circuit which generates the same logic level as a logic level at the third terminal at the fourth terminal.

### Claim 15 (depends on 10)

The device of claim 10, wherein
each of the semiconductor chips comprises:
first-side terminals including the first terminal at the first side; and
second-side terminals including the second terminal at the second side, and
the first-side terminals of each of a subset of the semiconductor chips excluding two of the semiconductor chips at both ends are coupled to the second-side terminals of another of the subset of the semiconductor chips on a one-to-one basis.

### Claim 16 (depends on 15)

The device of claim 15, wherein:
each of the semiconductor chips comprises a latch storing the same logic level as a logic level at the first terminal of that semiconductor chip.

### Claim 17 (depends on 16)

The device of claim 16, wherein
each of the semiconductor chips further comprises a controller which disables the logic circuit of that semiconductor chip after the latch of that semiconductor chip starts the storing of the same logic level as the logic level at the first terminal.

### Claim 18 (depends on 17)

The device of claim 17, wherein
the same logic level at the first and second terminals of each of the semiconductor chips is a low level.

### Claim 19

A semiconductor device comprising:
a substrate having a first surface and a second surface opposite to the first surface;
a first terminal on the first surface;
a second terminal on the second surface;
a logic circuit which generates a logic level of inversion of the logic level at the first terminal at the second terminal;
a latch storing the same logic level as the logic level at the first terminal; and
a controller which disables the logic circuit after the latch starts the storing of the same logic level as the logic level at the first terminal.

### Claim 20

A semiconductor device comprising:
semiconductor chips which are stacked and coupled through external terminals, wherein
while the semiconductor device is receiving a power supply and a chip enable signal which is negated, all the external terminals of the semiconductor chips are at the same logic level.