# US 2016/0259191 A1 · Manufacture method of tft array substrate and tft array substrate sturcture

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- Number: US 2016/0259191 A1
- Document ID: US20160259191A1
- Status: Published application
- Kind: A1
- Application number: 14/430,205
- Filed: 2014-09-11
- Published: 2016-09-08
- Earliest claimed: 2014-08-21
- Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Applicants: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Inventors: Bo SUN; Hongyuan XU; Hsiangchih HSIAO; Changi SU; Mian ZENG; Xiaoxiao WANG
- Web page: https://patentgrep.com/patent/US20160259191A1

## CPC

- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- G02F 1/133514: {Colour filters}
- G02F 1/134309: {characterised by their geometrical arrangement}
- G02F 1/13439: {characterised by their electrical, optical, physical properties; materials therefor; method of making}
- G02F 1/136: Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit (G02F1/135 takes precedence)
- G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer}
- H10D 30/0316: {of lateral bottom-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6732: {Bottom-gate only TFTs}
- H10D 30/6746: {Amorphous silicon}
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D 86/01: Manufacture or treatment
- H10D 86/021: {of multiple TFTs}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/411: {characterised by materials, geometry or structure of the substrates}
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/60: wherein the TFTs are in active matrices
- H10P 14/2922: {being non-crystalline insulating materials, e.g. glass or polymers}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3454: {Amorphous}
- H10P 14/44: Physical vapour deposition [PVD]
- H10P 76/204: {of organic photoresist masks}
- G02F 1/133302: {Rigid substrates, e.g. inorganic substrates}
- G02F 1/133519: {Overcoatings}
- G02F 1/136222: {Colour filters incorporated in the active matrix substrate}
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention provides a manufacture method of a TFT array substrate and a TFT array substrate structure, and the TFT array substrate structure comprises a substrate (1), a first metal electrode (2) on the substrate (1), a gate isolation layer (3) positioned on the substrate (1) and completely covering the first metal electrode (2), an island shaped semiconductor layer (4) on the gate isolation layer (3), a second metal electrode (6) on the gate isolation layer (3) and the island shaped semiconductor layer (4), a protecting layer (8) on the second metal electrode (6), a color resist layer (7) on the protecting layer (8), a protecting layer (12) on the color resist layer (7) and a first pixel electrode layer (9) on the protecting layer (12); a via (81) is formed on the protecting layer (8), the color resist layer (7) and the protecting layer (12), and an organic material layer (10) fills the inside of the via (81).

## Claims

### Claim 1

A manufacture method of a TFT array substrate, comprising steps of:
step 1, providing a substrate, and deposing and patterning a first metal layer on the substrate to form a first metal electrode;
step 2, forming a gate isolation layer and an island shaped semiconductor layer on the first metal electrode and the substrate;
step 3, deposing and patterning a second metal layer on the gate isolation layer and the island shaped semiconductor layer to form a second metal electrode;
step 4, deposing and patterning a protecting layer on the second metal electrode for forming the protecting layer;
step 5, coating a color resist layer on the protecting layer, and deposing and patterning a protecting layer on the color resist layer for forming the protecting layer, and forming a via on the protecting layer, the color resist layer and the protecting layer;
step 6, forming a pixel electrode layer and an organic material layer on the protecting layer and the second metal electrode.

### Claim 2 (depends on 1)

The manufacture method of the TFT array substrate according to claim 1, wherein the sixth step comprises:
step 61, deposing and patterning a first pixel electrode layer on the protecting layer and the second metal electrode for forming the first pixel electrode layer, and the first pixel electrode layer connects to the second metal electrode with the via;
step 62, coating the organic material layer on the first pixel electrode layer, and the organic material layer fills the via;
step 63, implementing developing process to remove the organic material layer outside the via.

### Claim 3 (depends on 1)

The manufacture method of the TFT array substrate according to claim 1, wherein the sixth step comprises:
step 611, deposing a first pixel electrode layer on the protecting layer and the second metal electrode;
step 612, coating the organic material layer on the first pixel electrode layer, and the organic material layer fills the via;
step 613, implementing developing process to remove the organic material layer around the via;
step 614, deposing a second pixel electrode layer on the first pixel electrode layer and the organic material layer;
step 615, patterning the first pixel electrode layer and the second pixel electrode layer at the same time with one photolithography process for forming the first pixel electrode layer and the second pixel electrode layer, and the first pixel electrode layer and the second pixel electrode layer connects to the second metal electrode with the via.

### Claim 4 (depends on 1)

The manufacture method of the TFT array substrate according to claim 1, wherein from the first step to the fourth step, a Physical Vapor Deposition or a Chemical Vapor Deposition is employed for deposing the first metal electrode, the gate isolation layer, the island shaped semiconductor layer, the second metal electrode and the protecting layers.

### Claim 5 (depends on 1)

The manufacture method of the TFT array substrate according to claim 1, wherein in the first step, the substrate is a glass substrate; in the second step, the island shaped semiconductor layer is formed with amorphous silicon, and the gate isolation layer and the island shaped semiconductor layer are sequentially formed by processes of film formation, exposure, development and etching.

### Claim 6 (depends on 1)

The manufacture method of the TFT array substrate according to claim 1, wherein in the fifth step, the color resist layer is a RGB color resist layer, and a diameter of a top of the via is 20 μm, and the organic material layer is formed with photoresist type material.

### Claim 7 (depends on 2)

The manufacture method of the TFT array substrate according to claim 2, wherein in the first step of the sixth step, a Physical Vapor Deposition is employed for deposing the first pixel electrode layer, and material of the first pixel electrode layer is ITO or IZO.

### Claim 8 (depends on 3)

The manufacture method of the TFT array substrate according to claim 3, wherein a Physical Vapor Deposition is employed for deposing the first pixel electrode layer and the second pixel electrode layer, and material of the first pixel electrode layer and the second pixel electrode layer is ITO or IZO.

### Claim 9

A TFT array substrate structure, comprising a substrate, a first metal electrode on the substrate, a gate isolation layer positioned on the substrate and completely covering the first metal electrode, an island shaped semiconductor layer on the gate isolation layer, a second metal electrode on the gate isolation layer and the island shaped semiconductor layer, a protecting layer on the second metal electrode, a color resist layer on the protecting layer, a protecting layer on the color resist layer and a first pixel electrode layer on the protecting layer; a via is formed on the protecting layer, the color resist layer and the protecting layer, and an organic material layer fills the inside of the via; the substrate is a glass substrate, and the island shaped semiconductor layer is formed with amorphous silicon, and the color resist layer is a RGB color resist layer, and material of the first pixel electrode layer is ITO or IZO, and the organic material layer is formed with photoresist type material.

### Claim 10 (depends on 9)

The TFT array substrate structure according to claim 9, further comprising a second pixel electrode layer on the first pixel electrode layer and the organic material layer, and material of the second pixel electrode layer is ITO or IZO.

### Claim 11

A TFT array substrate structure, comprising a substrate, a first metal electrode on the substrate, a gate isolation layer positioned on the substrate and completely covering the first metal electrode, an island shaped semiconductor layer on the gate isolation layer, a second metal electrode on the gate isolation layer and the island shaped semiconductor layer, a protecting layer on the second metal electrode, a color resist layer on the protecting layer, a protecting layer on the color resist layer and a first pixel electrode layer on the protecting layer; a via is formed on the protecting layer, the color resist layer and the protecting layer, and an organic material layer fills the inside of the via; the substrate is a glass substrate, and the island shaped semiconductor layer is formed with amorphous silicon, and the color resist layer is a RGB color resist layer, and material of the first pixel electrode layer is ITO or IZO, and the organic material layer is formed with photoresist type material;
the TFT array substrate structure further comprises a second pixel electrode layer on the first pixel electrode layer and the organic material layer, and material of the second pixel electrode layer is ITO or IZO.