# US 2016/0259003 A1 · Interface to full and reduced pin jtag devices

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- Number: US 2016/0259003 A1
- Document ID: US20160259003A1
- Status: Published application
- Kind: A1
- Application number: 15/159,171
- Filed: 2016-05-19
- Published: 2016-09-08
- Earliest claimed: 2006-10-18
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Lee D. Whetsel
- Web page: https://patentgrep.com/patent/US20160259003A1

## CPC

- G01R 31/31713: {Input or output interfaces for test, e.g. test pins, buffers (for scan test G01R31/318572)}
- G01R 31/2815: {Functional tests, e.g. boundary scans, using the normal I/O contacts (contacting devices G01R31/2808; testing digital circuits G01R31/317, G06F11/00)}
- G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)}
- G01R 31/3025: {Wireless interface with the DUT}
- G01R 31/31703: {Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193)}
- G01R 31/31725: {Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937)}
- G01R 31/31727: {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922)}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318558: {Addressing or selecting of subparts of the device under test}
- G01R 31/2851: {Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801)}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

## Claims

### Claim 1

A shadow protocol circuit comprising:
(a) a shadow protocol detection circuit having a test data in input, a test clock input, a test mode select input, an enable output, a command output, a command control output, a match input, an address output, and an address control output;
(b) a command circuit having a command input connected to the command output, a command control input connected to the command control output, a full pin select output, and a reduced pin select output; and
(c) an address circuit including:
i. a shift register having an address input coupled to the address output, an address clock input coupled to the address control output, and a shifted address output;
ii. an update register having an input coupled to the shifted address output, an address update input, and an update output;
iii. a device address circuit having a device address output; and
iv. comparator circuitry having an input coupled to the device address output, an input coupled to the update output, and a match output coupled to the match input.

### Claim 2 (depends on 1)

The shadow protocol circuit of claim 1 including a mode gate having one input connected to the test mode select input, and another input connected to the enable output.

### Claim 3 (depends on 1)

The shadow protocol circuit of claim 1 including a tri-state gate having one input connected to a test data out lead, an output connected to a gated test data out lead, and a control input connected to the enable output.