# US 2016/0259000 A1 · Communication and control topology for efficient testing of sets of devices

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- Number: US 2016/0259000 A1
- Document ID: US20160259000A1
- Status: Published application
- Kind: A1
- Application number: 14/637,533
- Filed: 2015-03-04
- Published: 2016-09-08
- Earliest claimed: 2015-03-04
- Assignees: Cavium, Inc.
- Applicants: Cavium, Inc.
- Inventors: Ethan Frederick Robbins
- Web page: https://patentgrep.com/patent/US20160259000A1

## CPC

- G01R 31/318555: {Control logic}
- G01R 31/31724: {Test controller, e.g. BIST state machine (for scan test G01R31/318555)}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318533: {using scanning techniques, e.g. LSSD, Boundary Scan, JTAG}
- G01R 31/318538: {Topological or mechanical aspects}
- G01R 31/318583: {Design for test}
- G01R 31/3187: Built-in tests
- G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)}
- G11C 29/16: using microprogrammed units, e.g. state machines
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 2029/0401: {in embedded memories}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A master controller includes: an interface to a CPU, an input port configured to receive a digital signal, and an output port configured to transmit a digital signal. Slave controllers each include: an interface to a device, an input port configured to receive a digital signal, and an output port configured to transmit a digital signal. A first chain bridge includes: a first set of input and output ports that couple the first chain bridge to a first chain of nodes each coupled to neighboring nodes by conductor paths in a closed loop, where the nodes of the first chain include the master controller, and a second set of input and output ports that couple the first chain bridge to a second chain of nodes each coupled to neighboring nodes by conductor paths in a closed loop, where the nodes of the second chain include multiple slave controllers.

## Claims

### Claim 1

An apparatus for testing devices coupled to respective slave controllers, the apparatus comprising:
at least one master controller, the master controller including:
an interface to a central processing unit,
an input port configured to receive a digital signal from a conductor path, and
an output port configured to transmit a digital signal to a conductor path;
a plurality of slave controllers, each slave controller including:
an interface to a device,
an input port configured to receive a digital signal from a conductor path, and
an output port configured to transmit a digital signal to a conductor path; and
a first chain bridge that includes:
a first set of input and output ports that couple the first chain bridge to a first chain of nodes each coupled to neighboring nodes by conductor paths in a closed loop, where the nodes of the first chain include the master controller, and
a second set of input and output ports that couple the first chain bridge to a second chain of nodes each coupled to neighboring nodes by conductor paths in a closed loop, where the nodes of the second chain include a plurality of slave controllers.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising a hierarchy of chains that includes:
the first chain at a root level of the hierarchy, the second chain at a first intermediate level below the root level, the nodes of the second chain including at least the first chain bridge coupling the second chain to the first chain, and a second chain bridge coupling the second chain to a third chain of nodes at a level below the first intermediate level, and
at one or more levels of the hierarchy below the first intermediate level, multiple chains of nodes each coupled to neighboring nodes by conductor paths in a closed loop, where the nodes of each chain of the multiple chains include one or more slave controllers and at least one chain bridge.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein at least two different chains of nodes include slave controllers that include interfaces to devices in different clock domains of an integrated circuit.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein at least two different chains of nodes include slave controllers that include interfaces to devices in different power domains of an integrated circuit.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein each slave controller includes:
a clock input port;
circuitry that receives a digital signal over an input port according to edges of clock signal provided at the clock input port; and
circuitry that transmits a digital signal over an output port according to edges of a clock signal provided at the clock input port.

### Claim 6 (depends on 5)

The apparatus of claim 5, further comprising a first clock circuit providing a first clock signal to each slave controller in the second chain.

### Claim 7 (depends on 6)

The apparatus of claim 6, further comprising a second clock circuit providing a second clock signal to each slave controller in a third chain of nodes, wherein the second clock signal has at least one of a different frequency or phase than the first clock signal.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein a chain bridge coupled to both the second chain and the third chain includes circuitry that translates messages between digital signals with aligned to the first clock signal and digital signals with edges aligned to the second clock signal.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the master controller is configured to provide poll messages that circulate around a chain, and the slave controllers are configured to provide poll response messages that circulate around a chain in response to a poll message after detecting an idle signal after the poll message.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the slave controllers are configured to circulate messages around a chain that correspond to status or control of a device coupled to its interface.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the master controller comprises a master memory controller, the slave controllers comprise slave memory controllers, and the devices comprise memory devices.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the messages include one or more of: a built-in self-test message, a built-in self-repair message, or an error-correcting code message.

### Claim 13

A non-transitory machine-readable medium storing a program for testing devices coupled to respective slave controllers, the program including instructions for causing a machine to:
simulate at least one master controller, the master controller including:
an interface to a central processing unit,
an input port configured to receive a digital signal from a conductor path, and
an output port configured to transmit a digital signal to a conductor path;
simulate a plurality of slave controllers, each slave controller including:
an interface to a device,
an input port configured to receive a digital signal from a conductor path, and
an output port configured to transmit a digital signal to a conductor path; and
simulate a first chain bridge that includes:
a first set of input and output ports that couple the first chain bridge to a first chain of nodes each coupled to neighboring nodes by conductor paths in a closed loop, where the nodes of the first chain include the master controller, and
a second set of input and output ports that couple the first chain bridge to a second chain of nodes each coupled to neighboring nodes by conductor paths in a closed loop, where the nodes of the second chain include a plurality of slave controllers.

### Claim 14 (depends on 13)

The medium of claim 13, further comprising instructions for causing the machine to simulate a hierarchy of chains that includes:
the first chain at a root level of the hierarchy,
the second chain at a first intermediate level below the root level, the nodes of the second chain including at least the first chain bridge coupling the second chain to the first chain, and a second chain bridge coupling the second chain to a third chain of nodes at a level below the first intermediate level, and
at one or more levels of the hierarchy below the first intermediate level, multiple chains of nodes each coupled to neighboring nodes by conductor paths in a closed loop, where the nodes of each chain of the multiple chains include one or more slave controllers and at least one chain bridge.

### Claim 15 (depends on 14)

The medium of claim 14, wherein at least two different chains of nodes include slave controllers that include interfaces to devices in different clock domains of an integrated circuit.

### Claim 16 (depends on 14)

The medium of claim 14, wherein at least two different chains of nodes include slave controllers that include interfaces to devices in different power domains of an integrated circuit.

### Claim 17 (depends on 13)

The medium of claim 13, wherein each slave controller includes:
a clock input port;
circuitry that receives a digital signal over an input port according to edges of clock signal provided at the clock input port; and
circuitry that transmits a digital signal over an output port according to edges of a clock signal provided at the clock input port.

### Claim 18 (depends on 17)

The medium of claim 17, further comprising instructions for causing the machine to simulate a first clock circuit providing a first clock signal to each slave controller in the second chain.

### Claim 19 (depends on 18)

The medium of claim 18, further comprising instructions for causing the machine to simulate a second clock circuit providing a second clock signal to each slave controller in a third chain of nodes, wherein the second clock signal has at least one of a different frequency or phase than the first clock signal.

### Claim 20 (depends on 19)

The medium of claim 19, wherein a chain bridge coupled to both the second chain and the third chain includes circuitry that translates messages between digital signals with aligned to the first clock signal and digital signals with edges aligned to the second clock signal.

### Claim 21 (depends on 13)

The medium of claim 13, wherein the master controller is configured to provide poll messages that circulate around a chain, and the slave controllers are configured to provide poll response messages that circulate around a chain in response to a poll message after detecting an idle signal after the poll message.

### Claim 22 (depends on 21)

The medium of claim 21, wherein the slave controllers are configured to circulate messages around a chain that correspond to status or control of a device coupled to its interface.

### Claim 23 (depends on 22)

The medium of claim 22, wherein the master controller comprises a master memory controller, the slave controllers comprise slave memory controllers, and the devices comprise memory devices.

### Claim 24 (depends on 23)

The medium of claim 23, wherein the messages include one or more of: a built-in self-test message, a built-in self-repair message, or an error-correcting code message.

### Claim 25

A method for testing design or fabrication of an integrated circuit that includes slave controllers for coupling to respective devices, the method comprising:
executing instructions corresponding to at least one master controller, the master controller including:
an interface to a central processing unit,
an input port configured to receive a digital signal from a conductor path, and
an output port configured to transmit a digital signal to a conductor path;
executing instructions corresponding to a plurality of slave controllers, each slave controller including:
an interface to a device,
an input port configured to receive a digital signal from a conductor path, and
an output port configured to transmit a digital signal to a conductor path; and
executing instructions corresponding to a first chain bridge that includes:
a first set of input and output ports that couple the first chain bridge to a first chain of nodes each coupled to neighboring nodes by conductor paths in a closed loop, where the nodes of the first chain include the master controller, and
a second set of input and output ports that couple the first chain bridge to a second chain of nodes each coupled to neighboring nodes by conductor paths in a closed loop, where the nodes of the second chain include a plurality of slave controllers.

### Claim 26 (depends on 25)

The method of claim 25, further comprising executing instructions corresponding to a hierarchy of chains that includes:
the first chain at a root level of the hierarchy,
the second chain at a first intermediate level below the root level, the nodes of the second chain including at least the first chain bridge coupling the second chain to the first chain, and a second chain bridge coupling the second chain to a third chain of nodes at a level below the first intermediate level, and at one or more levels of the hierarchy below the first intermediate level, multiple chains of nodes each coupled to neighboring nodes by conductor paths in a closed loop, where the nodes of each chain of the multiple chains include one or more slave controllers and at least one chain bridge.

### Claim 27 (depends on 26)

The method of claim 26, wherein at least two different chains of nodes include slave controllers that include interfaces to devices in different clock domains of an integrated circuit.

### Claim 28 (depends on 26)

The method of claim 26, wherein at least two different chains of nodes include slave controllers that include interfaces to devices in different power domains of an integrated circuit.

### Claim 29 (depends on 25)

The method of claim 25, wherein each slave controller includes:
a clock input port;
circuitry that receives a digital signal over an input port according to edges of clock signal provided at the clock input port; and
circuitry that transmits a digital signal over an output port according to edges of a clock signal provided at the clock input port.

### Claim 30 (depends on 29)

The method of claim 29, further comprising executing instructions corresponding to a first clock circuit providing a first clock signal to each slave controller in the second chain.

### Claim 31 (depends on 30)

The method of claim 30, further comprising executing instructions corresponding to a second clock circuit providing a second clock signal to each slave controller in a third chain of nodes, wherein the second clock signal has at least one of a different frequency or phase than the first clock signal.

### Claim 32 (depends on 31)

The method of claim 31, wherein a chain bridge coupled to both the second chain and the third chain includes circuitry that translates messages between digital signals with aligned to the first clock signal and digital signals with edges aligned to the second clock signal.

### Claim 33 (depends on 25)

The method of claim 25, wherein the master controller is configured to provide poll messages that circulate around a chain, and the slave controllers are configured to provide poll response messages that circulate around a chain in response to a poll message after detecting an idle signal after the poll message.

### Claim 34 (depends on 33)

The method of claim 33, wherein the slave controllers are configured to circulate messages around a chain that correspond to status or control of a device coupled to its interface.

### Claim 35 (depends on 34)

The method of claim 34, wherein the master controller comprises a master memory controller, the slave controllers comprise slave memory controllers, and the devices comprise memory devices.

### Claim 36 (depends on 35)

The method of claim 35, wherein the messages include one or more of: a built-in self-test message, a built-in self-repair message, or an error-correcting code message.