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US 2016/0254806 A1Published application
Comparator Apparatus and Method
AssigneeHuawei Technologies Co., Ltd.
InventorEuhan Chong
Life of this patent
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Abstract
A comparator comprises a differential input stage comprising a first n-type transistor and a second n-type transistor, an output stage coupled to the differential input stage, a clock transistor coupled to the differential input stage and a pre-charge apparatus connected in parallel with the clock transistor.
Claims20
A comparator comprising:
- a differential input stage comprising a first transistor and a second transistor, the first and second transistors configured to receive a differential input signal;
- an output stage coupled to the differential input stage, wherein the output stage is configured to amplify the differential input signal;
- a clock transistor connected between the differential input stage and a supply voltage;
- and
- a pre-charge apparatus connected in parallel with the clock transistor, wherein the pre-charge apparatus comprises a plurality of transistors connected in parallel and the pre-charge apparatus is configured to selectively bias the differential input stage by selectively turning on at least one transistor during a reset phase of the comparator.
2 more elements
A system comprising:
- a buffer configured to receive a differential signal and produce a buffered differential signal;
- and
- a receiver connected to the buffer, the receiver having a latch comparator comprising:
- a differential input stage configured to receive the buffered differential signal;
- an output stage coupled to the differential input stage, wherein the output stage is configured to amplify the buffered differential signal;
- a clock transistor connected between the differential input stage and a supply voltage;
- and
- a pre-charge apparatus connected in parallel with the clock transistor, wherein the pre-charge apparatus comprises a plurality of transistors connected in parallel and the pre-charge apparatus is configured to selectively bias the differential input stage by selectively turning on at least one transistor during a reset phase of the latch comparator.
5 more elements
A latch comparator comprising:
- a differential input stage comprising a first transistor and a second transistor, the first and second transistors configured to receive a differential input signal;
- an output stage coupled to the differential input stage, wherein the output stage is configured to amplify the differential input signal;
- a clock transistor connected between the differential input stage and a supply voltage, wherein a gate of the clock transistor is configured to receive a clock signal;
- and
- a pre-charge apparatus connected in parallel with the clock transistor, wherein the pre-charge apparatus comprises a plurality of transistors connected in parallel, and wherein at least one transistor of the plurality of transistors is configured to be turned on when the clock signal has a logic low state.
2 more elements
Dependencies are inferred from the claim text.