# US 2016/0254352 A1 · Reduced current leakage semiconductor device

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- Number: US 2016/0254352 A1
- Document ID: US20160254352A1
- Status: Published application
- Kind: A1
- Application number: 15/146,148
- Filed: 2016-05-04
- Published: 2016-09-01
- Earliest claimed: 2015-02-26
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Cheng-Wei Cheng; Pranita Kerber; Young-Hee Kim; Effendi Leobandung; Yanning Sun
- Web page: https://patentgrep.com/patent/US20160254352A1

## CPC

- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/10: Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D 62/102: {Constructional design considerations for preventing surface leakage or controlling electric field concentration}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 62/149: {Source or drain regions of field-effect devices}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 62/299: {having lateral doping variations (IGFETs having lightly doped source or drain extensions H10D30/601)}
- H10D 62/81: of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/854: further characterised by the dopants
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/05: using Group III-V technology
- H10P 14/2909: {Phosphides}
- H10P 14/3414: {being group IIIA-VIA materials}
- H10P 14/3421: {Arsenides}
- H10P 14/3438: {Doping during depositing}
- H10P 50/646: {of Group III-V materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate including a top surface;
a channel formed over the top surface of the substrate;
a halo layer that is epitaxially grown and covers a sidewall of the channel and a portion of the substrate that is lateral to the channel; and
a source or drain formed over the halo layer that is epitaxially grown;

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the halo layer provides an energy band barrier for the semiconductor device.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the halo layer comprises a first in-situ dopant and the source or drain comprises a second in-situ dopant that has an opposite doping polarity than the first in-situ dopant.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the source or drain is substantially free of amorphous regions.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the source or drain is substantially completely crystalline.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the channel comprises a group III material and a group V material.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the source or drain comprises a group III material and a group V material.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the halo layer substantially modifies a bandgap for the semiconductor device relative to a bandgap for a comparable device that does not include the halo layer.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the halo layer does not substantially modify a bandgap for the semiconductor device relative to a bandgap for a comparable device that does not include the halo layer.