# US 2016/0254346 A1 · Structures to avoid floating resurf layer in high voltage lateral devices

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- Number: US 2016/0254346 A1
- Document ID: US20160254346A1
- Status: Published application
- Kind: A1
- Application number: 14/634,801
- Filed: 2015-02-28
- Published: 2016-09-01
- Earliest claimed: 2015-02-28
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Yongxi Zhang; Philip L. Hower; John Lin; Guru Mathur; Scott G. Balster; Constantin Bulucea; Zachary K. Lee; Sameer P. Pendharkar
- Web page: https://patentgrep.com/patent/US20160254346A1

## CPC

- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 64/516: {the thicknesses being non-uniform}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate comprising p-type semiconductor material;
a lateral extended drain n-channel metal oxide semiconductor (LDNMOS) transistor, comprising:
a body of p-type semiconductor material disposed in the substrate; and
a drain drift region of n-type semiconductor material disposed in the substrate, the drain drift region extending laterally to the body;
a RESURF layer of p-type semiconductor material disposed in the substrate over at least a portion of the drain drift region, the RESURF layer extending from the drain drift region to a top surface of the substrate; and
a lateral shunt of p-type semiconductor material disposed in the substrate, the lateral shunt extending to the top surface of the substrate and extending laterally from the RESURF layer to the body.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the RESURF layer is 1 micron to 5 microns thick, and has an average doping density of 1×1016 cm−3 to 1×1017 cm−3.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the lateral shunt is 1 micron to 5 microns thick, and has an average doping density of 2×1016 cm−3 to 2×1017 cm−3.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the lateral shunt is 1 micron to 5 microns wide.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein a resistance of the lateral shunt is 1000 ohms to 10000 ohms.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, comprising a plurality of instances of the lateral shunt.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the LDNMOS transistor comprises a threshold adjustment region of p-type semiconductor disposed in the body.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the RESURF layer is laterally recessed adjacent to the lateral shunt by 1 micron to 2 microns.

### Claim 9

A semiconductor device, comprising:
a substrate comprising p-type semiconductor material;
an LDNMOS transistor, comprising:
a body of p-type semiconductor material disposed in the substrate; and
a drain drift region of n-type semiconductor material disposed in the substrate, the drain drift region extending laterally to the body;
a RESURF layer of p-type semiconductor material disposed in the substrate over at least a portion of the drain drift region, the RESURF layer extending from the drain drift region to a top surface of the substrate; and
a vertical shunt of p-type semiconductor material disposed in the substrate, the lateral shunt extending vertically through an opening in the drain drift region, from the RESURF layer to the p-type semiconductor material below the drain drift region.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the RESURF layer is 1 micron to 5 microns thick, and has an average doping density of 1×1016 cm−3 to 1×1017 cm−3.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein a width of the vertical shunt is 3 microns to 8 microns.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein a length of the vertical shunt is 3 microns to 10 microns.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the vertical shunt is laterally separated from the body by less than 3 microns.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, comprising a plurality of instances of the vertical shunt.

### Claim 15 (depends on 9)

The semiconductor device of claim 9, wherein a resistance of the vertical shunt is 5000 to 50000 ohms.

### Claim 16

A semiconductor device, comprising:
a substrate comprising p-type semiconductor material;
an LDNMOS transistor, comprising:
a body of p-type semiconductor material disposed in the substrate; and
a drain drift region of n-type semiconductor material disposed in the substrate, the drain drift region extending laterally to the body;
a RESURF layer of p-type semiconductor material disposed in the substrate over at least a portion of the drain drift region, the RESURF layer extending from the drain drift region to a top surface of the substrate; and
an interconnect shunt comprising a p-type shunt contact region in the substrate in an active area over the RESURF layer, a contact over the p-type shunt contact region, and a metal interconnect on the contact, the interconnect shunt extending from the RESURF layer to a source node of the LDNMOS transistor.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the RESURF layer is 1 micron to 5 microns thick, and has an average doping density of 1×1016 cm−3 to 1×1017 cm−3.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, wherein the interconnect shunt comprises metal silicide disposed on the shunt contact region under the contact.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, comprising a plurality of instances of the interconnect shunt.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, wherein the metal interconnect of the interconnect shunt comprises aluminum.