# US 2016/0254271 A1 · Non-volatile semiconductor memory device and manufacturing method thereof

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- Number: US 2016/0254271 A1
- Document ID: US20160254271A1
- Status: Published application
- Kind: A1
- Application number: 15/151,846
- Filed: 2016-05-11
- Published: 2016-09-01
- Earliest claimed: 2014-09-11
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Kabushiki Kaisha Toshiba
- Inventors: Yoshihiro AKUTSU; Ryota Katsumata
- Web page: https://patentgrep.com/patent/US20160254271A1

## CPC

- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10W 20/021: {of interconnections within wafers or substrates}
- H10W 20/066: {by forming silicides of refractory metals}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 90/00: Package configurations
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.

## Claims

### Claim 1

(canceled)

### Claim 2

A semiconductor memory device comprising:
an insulating layer;
a conductive layer provided above the insulating layer, the conductive layer having a first film and a second film provided on the first film, the first film including silicon and metal;
a stacked body provided above the conductive layer and including a plurality of electrode layers separately stacked in a first direction;
a first semiconductor body provided in the stacked body and extending in the first direction, the first semiconductor body electrically connected to the conductive layer;
a memory portion provided between the first semiconductor body and one of the plurality of electrode layers; and
a source layer extending in the first direction and in contact with the conductive layer.

### Claim 3 (depends on 2)

The device according to claim 2, wherein the second film includes silicon and impurity.

### Claim 4 (depends on 2)

The device according to claim 2, wherein the first film is a silicide layer of the silicon and the metal.

### Claim 5 (depends on 2)

The device according to claim 2, wherein the metal is Ni or Co.

### Claim 6 (depends on 3)

The device according to claim 3, wherein the impurity is boron.

### Claim 7 (depends on 2)

The device according to claim 2, further comprising an isolation layer extending in the first direction, the isolation layer being in contact with the first film.

### Claim 8 (depends on 2)

The device according to claim 2, wherein the source layer is in contact with the first film.