# US 2016/0254263 A1 · Methods and apparatuses including an active area of a tap intersected by a boundary of a well

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- Number: US 2016/0254263 A1
- Document ID: US20160254263A1
- Status: Published application
- Kind: A1
- Application number: 15/149,774
- Filed: 2016-05-09
- Published: 2016-09-01
- Earliest claimed: 2014-09-30
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Michael Smith
- Web page: https://patentgrep.com/patent/US20160254263A1

## CPC

- H10D 84/859: {comprising both N-type and P-type wells, e.g. twin-tub}
- H10B 12/50: {Peripheral circuit region structures}
- H10D 62/125: {Shapes of junctions between the regions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/60: Impurity distributions or concentrations
- H10D 84/0191: {Manufacturing their doped wells}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. A boundary of the well intersects an active area of a tap to the well.

## Claims

### Claim 1

An apparatus comprising:
a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity;
a tap to the well, wherein an active area of the tap is over both the well and the semiconductor structure.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the semiconductor structure comprises a P-well, the well comprises an N-well, and the tap comprises an N+ area and a N-area.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the semiconductor structure comprises a N-well, the well comprises an P-well, and the tap comprises an P+ area and a P-area.

### Claim 4

An apparatus comprising:
a memory array comprising a plurality of memory cells; and
support circuitry coupled to the memory array, the support circuitry comprising a semiconductor device comprising
a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity; and
a tap to the well, wherein an active area of the tap is not fully within a boundary of the well.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the memory array and the support circuitry are included in a memory device.

### Claim 6 (depends on 5)

The apparatus of claim 5, further comprising a processor coupled to the memory device.