# US 2016/0254237 A1 · Radio-frequency (rf) shielding in fan-out wafer level package (fowlp) > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2016/0254237 A1 - Document ID: US20160254237A1 - Status: Published application - Kind: A1 - Application number: 14/634,148 - Filed: 2015-02-27 - Published: 2016-09-01 - Earliest claimed: 2015-02-27 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Daeik Daniel KIM; David Francis BERDY; Mario Francisco VELEZ; Changhan Hobie YUN; Chengjie ZUO; Jonghae KIM; Matthew Michael NOWAK - Web page: https://patentgrep.com/patent/US20160254237A1 ## CPC - H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/611: {for connecting multiple chips together} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 72/00: Interconnections or connectors in packages - H10W 72/0198: {batch processes} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 90/00: Package configurations - H10W 72/9413: {on encapsulations} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a fan-out wafer level package (FOWLP) module or device. Intra-module shielding between individual chips within the FOWLP module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a FOWLP to ensure reliable grounding. ## Claims ### Claim 1 A device, comprising: a fan-out wafer level package (FOWLP) comprising at least one conductor portion and at least one insulator portion; a first chip comprising a first plurality of contacts, the first chip positioned in direct contact with the FOWLP; a second chip comprising a second plurality of contacts, the second chip positioned in direct contact with the FOWLP, the first chip and the second chip spaced apart by a gap, and the at least one conductor portion of the FOWLP positioned directly opposite the gap between the first chip and the second chip; and a conductor shield comprising a plurality of conductor surfaces, at least one of the conductor surfaces directly connected to the at least one conductor portion of the FOWLP directly opposite the gap between the first chip and the second chip, at least one of the conductor surfaces immediately surrounding the first chip, and at least one of conductor surfaces immediately surrounding the second chip, wherein a bottom surface of the first chip including bottom surfaces of the first plurality of contacts, a bottom surface of the second chip including bottom surfaces of the second plurality of contacts, and the at least one of the conductor surfaces directly connected to the at least one conductor portion of the FOWLP directly opposite the gap between the first chip and the second chip are substantially flush with each other. ### Claim 2 (depends on 1) The device of claim 1, wherein the FOWLP comprises an interposing FOWLP. ### Claim 3 (depends on 2) The device of claim 2, wherein the interposing FOWLP comprises a plurality of dielectric portions and a plurality of conductor portions. ### Claim 4 (depends on 3) The device of claim 3, wherein the dielectric portions of the interposing FOWLP include the at least one insulator portion of the FOWLP, and wherein the conductor portions of the interposing FOWLP include the at least one conductor portion of the FOWLP. ### Claim 5 (depends on 1) The device of claim 1, wherein the first and second pluralities of contacts comprise conductive contacts. ### Claim 6 (depends on 1) The device of claim 1, wherein the FOWLP comprises a plurality of conductor portions including the at least one conductor portion, and wherein at least some of the first and second pluralities of contacts are directly connected to at least some of the conductor portions of the FOWLP. ### Claim 7 (depends on 1) The device of claim 1, wherein the FOWLP comprises a plurality of insulator portions including the at least one insulator portion, wherein the first chip is directly connected to at least one of the insulator portions of the FOWLP, and wherein the second chip is directed connected to at least another one of the insulator portions of the FOWLP. ### Claim 8 (depends on 1) The device of claim 1, further comprising a mold disposed on the conductor shield. ### Claim 9 (depends on 8) The device of claim 8, wherein the mold is separated from the first and second chips by the conductor shield. ### Claim 10 A device, comprising: a fan-out wafer level package (FOWLP) comprising a plurality of conductor portions and a plurality of dielectric portions, the FOWLP having a substantially flat first surface over the conductor portions and the dielectric portions; a first chip comprising a first plurality of contacts in direct contact with the FOWLP; a second chip comprising a second plurality of contacts in direct contact with the FOWLP, the first chip and the second chip spaced apart by a gap, and at least one of the conductor portions of the FOWLP positioned directly opposite the gap between the first chip and the second chip; and a conductor shield comprising a plurality of conductor surfaces, at least one of the conductor surfaces directly connected to the at least one of the conductor portions of the FOWLP directly opposite the gap between the first chip and the second chip, at least one of the conductor surfaces immediately surrounding the first chip, and at least one of the conductor surfaces immediately surrounding the second chip, wherein a bottom surface of the first chip including bottom surfaces of the first plurality of contacts, a bottom surface of the second chip including bottom surfaces of the second plurality of contacts, and the at least one of the conductor surfaces directly connected to the at least one of the conductor portions of the FOWLP directly opposite the gap between the first chip and the second chip are substantially flush with each other. ### Claim 11 (depends on 10) The device of claim 10, wherein the first and second pluralities of contacts comprise conductive contacts. ### Claim 12 (depends on 10) The device of claim 10, wherein at least some of the first and second pluralities of contacts are directly connected to at least some of the conductor portions of the FOWLP. ### Claim 13 (depends on 10) The device of claim 10, wherein the first chip is directly connected to at least one of the dielectric portions of the FOWLP, and wherein the second chip is directed connected to at least another one of the dielectric portions of the FOWLP. ### Claim 14 (depends on 10) The device of claim 10, further comprising a mold disposed on the conductor shield. ### Claim 15 (depends on 14) The device of claim 14, wherein the mold is separated from the first and second chips by the conductor shield. ### Claim 16 A device, comprising: a fan-out wafer level package (FOWLP) comprising a plurality of conductor portions and a plurality of insulator portions, the FOWLP having a substantially flat first surface over the conductor portions and the insulator portions; a first chip comprising a first plurality of contacts in direct contact with the FOWLP; a second chip comprising a second plurality of contacts in direct contact with the FOWLP, wherein the first chip and the second chip are spaced apart by a gap, and wherein at least one of the conductor portions of the FOWLP is positioned directly opposite the gap between the first chip and the second chip; and means for ground shielding the first chip and the second chip, wherein a bottom surface of the first chip including bottom surfaces of the first plurality of contacts and a bottom surface of the second chip including bottom surfaces of the second plurality of contacts are substantially flush with each other. ### Claim 17 (depends on 16) The device of claim 16, wherein the means for ground shielding the first chip and the second chip comprises a conductor shield comprising a plurality of conductor surfaces, wherein at least one of the conductor surfaces is directly connected to the at least one of the conductor portions of the FOWLP directly opposite the gap between the first chip and the second chip, wherein at least one of the conductor surfaces immediately surrounds the first chip, and wherein at least one of the conductor surfaces immediately surrounds the second chip. ### Claim 18 (depends on 16) The device of claim 16, wherein the first and second pluralities of contacts comprise conductive contacts. ### Claim 19 (depends on 16) The device of claim 16, wherein at least some of the first and second pluralities of contacts are directly connected to at least some of the conductor portions of the FOWLP. ### Claim 20 (depends on 16) The device of claim 16, wherein the first chip is directly connected to at least one of the insulator portions of the FOWLP, and wherein the second chip is directed connected to at least another one of the insulator portions of the FOWLP. ### Claim 21 (depends on 16) The device of claim 16, wherein the FOWLP comprises an interposing FOWLP. ### Claim 22 (depends on 16) The device of claim 16, further comprising a mold disposed on the means for ground shielding. ### Claim 23 (depends on 22) The device of claim 22, wherein the mold is separated from the first and second chips by the means for ground shielding. ### Claim 24 A method of making a device, comprising: providing a reconstitution tape having a first surface; providing a first plurality of contacts and a second plurality of contacts on the first surface of the reconstitution tape; providing a first chip having a first plurality of contact openings to receive the first plurality of contacts on the first surface of the reconstitution tape; providing a second chip having a second plurality of contact openings to receive the second plurality of contacts on the first surface of the reconstitution tape, wherein the first chip and the second chip are spaced apart by a gap exposing at least one portion of the first surface of the reconstitution tape; and providing a conductor shield comprising a plurality of conductor surfaces, wherein at least one of the conductor surfaces is in direct contact with the at least one portion of the first surface of the reconstitution tape exposed by the gap between the first chip and the second chip, wherein at least one of the conductor surfaces immediately surrounds the first chip, and wherein at least one of conductor surfaces immediately surrounds the second chip. ### Claim 25 (depends on 24) The method of claim 24, wherein the providing a conductor shield comprises providing conformal shielding with a metal on the first chip, on the second chip, and on the at least one portion of the first surface of the reconstitution tape exposed by the gap between the first chip and the second chip. ### Claim 26 (depends on 24) The method of claim 24, further comprising providing a molding outside the conductor shield. ### Claim 27 (depends on 24) The method of claim 24, further comprising removing the reconstitution tape to expose a first surface of the first chip including the first plurality of contacts, a first surface of the second chip including the second plurality of contacts, and the at least one of the conductor surfaces of the conductor shield between the first chip and the second chip. ### Claim 28 (depends on 27) The method of claim 27, further comprising providing an interposing fan-out wafer level package (FOWLP) on the first surface of the first chip including the first plurality of contacts, on the first surface of the second chip including the second plurality of contacts, and on the at least one of the conductor surfaces of the conductor shield between the first chip and the second chip. ### Claim 29 (depends on 28) The method of claim 28, wherein the interposing FOWLP comprises a plurality of conductor portions and a plurality of dielectric portions, and wherein at least some of the conductor portions of the interposing FOWLP are directly connected to at least some of the first and second pluralities of contacts of the first and second chips. ### Claim 30 (depends on 28) The method of claim 28, wherein the providing an interposing FOWLP comprises providing the interposing FOWLP by a redistribution layer (RDL) process.