# US 2016/0254221 A1 · Semiconductor package and manufacturing method thereof

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- Number: US 2016/0254221 A1
- Document ID: US20160254221A1
- Status: Published application
- Kind: A1
- Application number: 15/052,219
- Filed: 2016-02-24
- Published: 2016-09-01
- Earliest claimed: 2015-02-25
- Assignees: Amkor Technology, Inc.
- Applicants: Amkor Technology, Inc.
- Inventors: In Ho Kim; Jae Yun Kim; Kyeong Sool Seong
- Web page: https://patentgrep.com/patent/US20160254221A1

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/90: Bond pads, in general
- H10W 70/654: Top-view layouts
- H10W 70/656: Fan-in layouts
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/981: {Auxiliary members, e.g. spacers}
- H10W 72/983: {Reinforcing structures, e.g. collars}
- H10W 74/147: {the encapsulations being multilayered}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package and a method of making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor packages, and methods of making thereof, that comprise a conductive layer that comprises an anchor portion extending through at least one dielectric layer.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor die comprising a die passivation layer and a conductive pad exposed through an aperture in the die passivation layer;
a first dielectric layer (DL) on the die passivation layer and comprising:
a first DL aperture through which the conductive pad is exposed; and
a second DL aperture through which the die passivation layer is exposed;
a conductive layer (CL) on the first dielectric layer and comprising:
a first CL portion in the first DL aperture;
a second CL portion in the second DL aperture; and
a third CL portion;
a second dielectric layer (DL) on the conductive layer and comprising a third DL aperture through which the third CL portion is exposed; and
an interconnection structure electrically connected to the third CL portion through the third DL aperture.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first CL portion comprises a pad region, the second CL portion comprises an anchor region, and the third CL portion comprises a bump region

### Claim 3 (depends on 1)

The semiconductor device of claim 1, comprising an under bump metallization (UBM) structure between the third CL portion and the interconnection structure.

### Claim 4 (depends on 3)

The semiconductor package of claim 3, wherein at least a portion of the second CL portion is positioned outside a footprint of the UBM structure.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the second CL portion contacts the die passivation layer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the second CL portion surrounds the third CL portion.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the second CL portion comprises a dimple on a side of the second CL portion opposite the semiconductor die.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein a portion of the second dielectric layer is in the dimple.

### Claim 9

A semiconductor device comprising:
a conductive pad;
a first dielectric layer (DL) comprising a first DL aperture through which the conductive pad is exposed;
a second dielectric layer (DL) on the first dielectric layer and comprising a plurality of DL anchor apertures through which the first dielectric layer is exposed;
a conductive layer (CL) on the second dielectric layer and comprising a plurality of CL anchor portions, each in a respective one of the DL anchor apertures; and
a third dielectric layer (DL) on the conductive layer and comprising a DL aperture through which a portion of the conductive layer is exposed.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, comprising a semiconductor die, wherein the conductive pad is a pad of the semiconductor die and the first dielectric layer is a passivation layer of the semiconductor die.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein none of the plurality of CL anchor portions makes electrical contact with a semiconductor die through its respective DL anchor aperture.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, comprising an under bump metallization (UBM) structure on the portion of the conductive layer exposed through the aperture in the third dielectric layer.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein at least a portion of each of the plurality of CL anchor portions is positioned outside a footprint of the UBM structure.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein the plurality of CL anchor portions surround the portion of the conductive layer exposed through the DL aperture in the third dielectric layer.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein each of the plurality of CL anchor portions is circular.

### Claim 16

A semiconductor device comprising:
a first dielectric layer (DL);
second dielectric layer (DL) comprising an anchor aperture exposing the first dielectric layer; and
a conductive layer (CL) on the second dielectric layer and comprising:
a first CL end region electrically contacting another conductive layer;
a second CL end region electrically contacting an interconnection structure of the semiconductor device;
an extension region extending between the first and second CL end regions; and
an anchor region in the anchor aperture and contacting the first DL.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the first dielectric layer is a passivation layer of a semiconductor die.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, comprising an under bump metallization (UBM) structure between the second CL end region and the interconnection structure.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, wherein:
the second dielectric layer comprises a plurality of additional anchor apertures exposing the first dielectric layer; and
the conductive layer comprises a plurality of additional anchor regions, each in a respective one of the additional anchor apertures.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the anchor region and the plurality of additional anchor regions surround the second CL end region.