# US 2016/0253285 A1 · Method And System of Synchronizing Processors To The Same Computational Point

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2016/0253285 A1
- Document ID: US20160253285A1
- Status: Published application
- Kind: A1
- Application number: 15/148,271
- Filed: 2016-05-06
- Published: 2016-09-01
- Earliest claimed: 2014-01-08
- Assignees: Artesyn Embedded Computing, Inc.
- Applicants: Artesyn Embedded Computing, Inc.
- Inventors: Shugao YE; Liu JIANG; Kai HU; Martin Peter John CORNES; Pasi Jukka Petteri VAANANEN
- Web page: https://patentgrep.com/patent/US20160253285A1

## CPC

- G06F 15/17325: {Synchronisation; Hardware support therefor (intertask synchronisation G06F9/52)}
- G06F 9/522: {Barrier synchronisation}
- G06F 12/06: Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence)
- G06F 2212/657: Virtual address space management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A system for synchronizing central processing units (CPU) includes a schedule module that communicates a synchronization point, a first CPU that writes a first memory address to a first register in response to the first CPU reaching the synchronization point, and a second CPU that writes a second memory address to a second register in response to the second CPU reaching the synchronization point. The system further includes a first logical AND module that writes a first value to a third register based on the first and second memory addresses and a second logical AND module that writes a second value to a fourth register based on the first and second memory addresses. The system also includes a scheduler module that selectively generates a processor sync signal based on the first and second value.

## Claims

### Claim 1

A method for synchronizing central processing units (CPU) comprising:
generating a first synchronization message at a synchronization point;
generating a second synchronization message at the synchronization point;
communicating the first synchronization message;
communicating the second synchronization message;
determining whether the second synchronization message was communicated;
determining whether the first synchronization message was communicated; and
determining whether to execute a plurality of tasks based on the first and second synchronization messages.

### Claim 2 (depends on 1)

The method of claim 1 further comprising determining a first CPU and a second CPU are synchronized based on the first and second synchronization messages.

### Claim 3 (depends on 2)

The method of claim 2 further comprising determining the first CPU and the second CPU are synchronized when the first synchronization message is generated and the second synchronization message is received.

### Claim 4 (depends on 3)

The method of claim 3 further comprising generating a first processor synchronization signal in response to the determination that the first CPU and the second CPU are synchronized.

### Claim 5 (depends on 4)

The method of claim 4 further comprising further comprising determining the first CPU and the second CPU are synchronized when the second synchronization message is generated and the first synchronization message is received.

### Claim 6 (depends on 5)

The method of claim 5 further comprising generating a second processor synchronization signal in response to the determination that the first CPU and the second CPU are synchronized.

### Claim 7 (depends on 6)

The method of claim 6 further comprising executing the plurality of tasks in response to receiving the first processor synchronization signal and the second synchronization signal.

### Claim 8 (depends on 6)

The method of claim 6 further comprising not executing the plurality of tasks in response to not receiving at least one of the first and second synchronization signals.

### Claim 9 (depends on 1)

The method of claim 1 further comprising incrementing a synchronization counter in response to not receiving at least one of the first and second synchronization messages.

### Claim 10 (depends on 9)

The method of claim 9 further comprising selectively determining whether to restart a first CPU and a second CPU in response to the synchronization counter being greater than a predetermined threshold.