# US 2016/0253271 A1 · Memory data security > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2016/0253271 A1 - Document ID: US20160253271A1 - Status: Published application - Kind: A1 - Application number: 14/632,025 - Filed: 2015-02-26 - Published: 2016-09-01 - Earliest claimed: 2015-02-26 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary; Timothy J. Dell - Web page: https://patentgrep.com/patent/US20160253271A1 ## CPC - G06F 12/1433: {for a module or a part of a module} - G06F 1/3296: by lowering the supply or operating voltage - G06F 21/6245: {Protecting personal data, e.g. for financial or medical purposes} - G06F 2212/1052: Security improvement - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory module secures data stored on the memory module. A request for the data from a computer system is received by the memory module. A verification key from the computer system is also received by the memory module. A reference key is retrieved by the memory module, the reference key is stored on the memory module. A comparison status is generated by the memory module by comparing the verification key with the reference key. A response is sent to the computer by the memory module that is dependent upon the comparison status. ## Claims ### Claim 1 A method for securing data on at least one memory chip of a memory module, the method comprising: receiving, by the memory module, a request for the data from a computer system; receiving, by the memory module, a verification key from the computer system; retrieving, by the memory module, a reference key, the reference key stored on the memory module; generating, by the memory module, a comparison status in response to comparing the verification key with the reference key; and sending, by the memory module, a response to the computer system in response to the comparison status. ### Claim 2 (depends on 1) The method of claim 1, wherein the response is the data from the at least one memory chip and the comparison status is that the verification key and the reference key match. ### Claim 3 (depends on 1) The method of claim 1, wherein the response is false data and the comparison status is that the verification key and the reference key do not match. ### Claim 4 (depends on 3) The method of claim 3, wherein the false data is selected from the group consisting of all zeros, all ones, random characters, and nothing. ### Claim 5 (depends on 1) The method of claim 1, wherein the response is the serial number of the memory module and the comparison status is that the verification key and the reference key match. ### Claim 6 (depends on 1) The method of claim 1, wherein the response is the status of the memory module and the comparison status is that the verification key and the reference key match. ### Claim 7 (depends on 1) The method of claim 1, wherein the reference key is comprised of a first set of one or more voltages, and wherein the verification key is comprised of a second set of one or more voltages, and wherein the comparison status is generated by outputting electrical energy based on the first set of voltages and the second set of voltages. ### Claim 8 A memory module for securing data stored on a memory module, the memory module comprising: at least one memory chip configured to store the data; a communication bus configured to receive a request for the data from a computer system, the communication bus configured to transmit the request for the data to the at least one memory chip, the communication bus further configured to receive a verification key from the computer system; a reference chip configured to store a reference key related to the memory module; a comparison chip configured to receive the verification key from the communication bus, the comparison chip further configured to receive the reference key from the reference chip, the comparison chip further configured to generate a comparison status in response to comparing the verification key and the reference key; and a logic chip configured to receive the data from the at least one memory chip, the logic chip further configured to receive the comparison status from the comparison chip, the logic chip further configured to send a response to the communication bus in response to the comparison status. ### Claim 9 (depends on 8) The memory module of claim 8, wherein the response is the data from the at least one memory chip and the comparison status is that the verification key and the reference key match. ### Claim 10 (depends on 8) The memory module of claim 8, wherein the response is false data and the comparison status is that the verification key and the reference key do not match. ### Claim 11 (depends on 10) The memory module of claim 10, wherein the false data is selected from the group consisting of all zeros, all ones, random characters, and nothing. ### Claim 12 (depends on 8) The memory module of claim 8, wherein the response is the serial number of the memory module and the comparison status is that the verification and the reference key match. ### Claim 13 (depends on 8) The memory module of claim 8, wherein the response is the status of the memory module and the comparison status is that the verification and the reference key match. ### Claim 14 (depends on 8) The memory module of claim 8, wherein the reference key is comprised of a first set of one or more voltages, and wherein the verification key is comprised of a second set of one or more voltages, and wherein the comparison status is generated by outputting electrical energy based on the first set of voltages and the second set of voltages. ### Claim 15 (depends on 8) The memory module of claim 8, wherein the reference chip is a vital product data chip further configured to store an identification number, the identification number corresponding to the memory module. ### Claim 16 (depends on 8) The memory module of claim 8, wherein the logic chip is located inside the at least one memory chip. ### Claim 17 A system for securing data, the system comprising: a processor; a memory controller configured to receive a request for the data from the processor; and a memory module comprising: at least one memory chip configured to store the data; a communication bus configured to receive the request and a verification key from the memory controller, transmit the request to the memory chip, and send a response to the memory controller; a reference chip configured to store a reference key related to the memory module; a comparison chip configured to receive the verification key from the communication bus, receive the reference key from the reference chip, and generate a comparison status in response to comparing the verification key and the reference key; and a logic chip configured to receive the data from the memory chip, receive the comparison status from the comparison chip, generate, based on the comparison status, a response, and transmit the response to the communication bus. ### Claim 18 (depends on 17) The system of claim 17, wherein the response is the data from the at least one memory chip and the comparison status is that the verification key and the reference key match. ### Claim 19 (depends on 17) The system of claim 17, wherein the response is false data and the comparison status is that the verification key and the reference key do not match. ### Claim 20 (depends on 19) The system of claim 19, wherein the false data is selected from the group consisting of all zeros, all ones, random characters, and nothing.