# US 2016/0253233 A1 · Watchdog Timer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2016/0253233 A1 - Document ID: US20160253233A1 - Status: Published application - Kind: A1 - Application number: 15/053,504 - Filed: 2016-02-25 - Published: 2016-09-01 - Earliest claimed: 2015-02-27 - Assignees: Microchip Technology Incorporated - Applicants: Microchip Technology Incorporated - Inventors: Keith Curtis - Web page: https://patentgrep.com/patent/US20160253233A1 ## CPC - G06F 11/0757: {by exceeding a time limit, i.e. time-out, e.g. watchdogs} - G06F 11/0721: {within a central processing unit [CPU]} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A microcontroller may comprise a central processing unit coupled with a plurality of peripheral devices through a system bus; and a watchdog timer unit receiving a clear watchdog signal and being configured to generate a watchdog timeout signal for resetting the microcontroller, wherein the watchdog timer unit is further configured to define a first and a second watchdog timeout period through a first and a second timer, respectively, further having logic to select the first or the second timer, wherein the clear watchdog signal resets the first and second timer. ## Claims ### Claim 1 A watchdog timer unit configured to define a first and a second watchdog time period, wherein the watchdog timer unit is configured, after activation of the watchdog timer unit, to automatically select the first watchdog time period until a first clear watchdog signal has been received whereupon the watchdog timer unit switches to the second watchdog time period. ### Claim 2 (depends on 1) The watchdog timer unit according to claim 1, wherein the first watchdog time period is endless. ### Claim 3 (depends on 2) The watchdog timer unit according to claim 2, further comprising a flip-flop being controlled by the clear watchdog signal and having an output controlling a switch that couples a reset output of the watchdog timer unit with either the output of a timer or a logic 1. ### Claim 4 (depends on 1) The watchdog timer unit according to claim 1, wherein the first watchdog time period is defined by a first timer and the second watchdog time period is defined by a second timer, wherein a first clear watchdog signal switches the watchdog timer unit from the first timer to the second timer. ### Claim 5 (depends on 4) The watchdog timer unit according to claim 4, further comprising a flip-flop being controlled by the clear watchdog signal and having an output controlling a switch that couples a reset output of the watchdog timer unit with either the output of the first or second timer. ### Claim 6 (depends on 1) The watchdog timer unit according to claim 1, wherein the first watchdog time period is defined by a first preset value stored in a first register and the second watchdog time period is defined by a second preset value stored in a second register, wherein upon activation of the watchdog timer unit the first register is selected through a switch to preset a watchdog timer and a first clear watchdog signal switches the switch to the second register providing the second preset value to the watchdog timer. ### Claim 7 (depends on 1) The watchdog timer unit according to claim 1, wherein the first watchdog time period is defined by a first clock signal fed to the watchdog timer unit and the second watchdog time period is defined by a second clock signal fed to the watchdog timer unit, wherein upon activation of the watchdog timer unit the first clock signal is selected to clock a watchdog timer and a first clear watchdog signal causes selection of the second clock signal to clock the watchdog timer. ### Claim 8 (depends on 1) The watchdog timer unit according to claim 1, comprising a timer configured to be preset through a preset register in a first mode or in a second mode directly thereby bypassing the preset register, wherein upon activation of the watchdog timer unit the timer is preset directly with a first preset value and upon receipt of a first any following clear watchdog signals, the timer is preset through the preset register. ### Claim 9 (depends on 8) The watchdog timer unit according to claim 8, wherein the timer is preset directly through a central processing unit. ### Claim 10 (depends on 8) The watchdog timer unit according to claim 8, wherein the timer is preset directly through a start-up configuration register. ### Claim 11 A microcontroller comprising: a central processing unit coupled with a plurality of peripheral devices through a system bus; and a watchdog timer unit receiving a clear watchdog signal and being configured to generate a watchdog timeout signal for resetting the microcontroller, wherein the watchdog timer unit is further configured to define a first and a second watchdog timeout period through a first and a second timer, respectively, further comprising logic to select the first or the second timer, wherein the clear watchdog signal resets the first and second timer. ### Claim 12 (depends on 11) The microcontroller according to claim 11, wherein activation of the watchdog timer unit is performed automatically when the microcontroller is powered up thereby selecting the first timer and after receipt of a first watchdog timer timeout signal generated by the first timer, the watchdog timer unit is configured to switch to the second timer. ### Claim 13 (depends on 11) The microcontroller according to claim 11, further comprising an inverter coupled with an output of the second timer, wherein the watchdog timer unit further receives a power fail signal, wherein the logic is further configured to select between the first timer, the second timer and the output of the inverter, and wherein the watchdog timer unit selects the output of the inverter when a clear watchdog signal and a power fail signal is received. ### Claim 14 (depends on 12) The microcontroller according to claim 12, wherein the first watchdog time period is endless. ### Claim 15 (depends on 12) The microcontroller according to claim 12, further comprising a flip-flop being controlled by the clear watchdog signal and having an output controlling a switch that couples a reset output of the watchdog timer unit with either the output of a timer or a logic 1. ### Claim 16 (depends on 11) The microcontroller according to claim 11, wherein the first watchdog time period is defined by a first timer and the second watchdog time period is defined by a second timer, wherein a first clear watchdog signal switches the watchdog timer unit from the first timer to the second timer. ### Claim 17 (depends on 16) The microcontroller according to claim 16, further comprising a clock generating unit configured to generate a first clock fed to the first timer and a second clock fed to the second timer. ### Claim 18 (depends on 16) The microcontroller according to claim 16, further comprising a flip-flop being controlled by the clear watchdog signal and having an output controlling a switch that couples a reset output of the watchdog timer unit with either the output of the first or second timer. ### Claim 19 (depends on 11) The microcontroller according to claim 11, wherein the first watchdog time period is defined by a first preset value stored in a first register and the second watchdog time period is defined by a second preset value stored in a second register, wherein upon activation of the watchdog timer unit the first register is selected through a switch to preset a watchdog timer and a first clear watchdog signal switches the switch to the second register providing the second preset value to the watchdog timer. ### Claim 20 (depends on 11) The microcontroller according to claim 11, comprising a clock generating unit configured to generate a first clock signal and a second clock signal, wherein the first watchdog time period is defined by the first clock signal fed to the watchdog timer unit and the second watchdog time period is defined by the second clock signal fed to the watchdog timer unit, wherein upon activation of the watchdog timer unit the first clock signal is selected to clock a watchdog timer and a first clear watchdog signal causes selection of the second clock signal to clock the watchdog timer. ### Claim 21 (depends on 11) The microcontroller according to claim 11, comprising a timer configured to be preset through a preset register in a first mode or in a second mode directly thereby bypassing the preset register, wherein upon activation of the watchdog timer unit the timer is preset directly with a first preset value and upon receipt of a first any following clear watchdog signals, the timer is preset through the preset register. ### Claim 22 (depends on 21) The microcontroller according to claim 21, wherein the timer is preset directly through the central processing unit. ### Claim 23 (depends on 21) The microcontroller according to claim 21, wherein the timer is preset directly through a start-up configuration register of the microcontroller. ### Claim 24 A method for monitoring the execution of a program in a microcontroller through a watchdog timer unit defining a time period which after expiration resets the microcontroller wherein expiration of the time period is prevented by periodically resetting the watchdog timer unit, the method comprising: after activation of the watchdog timer unit, the watchdog timer unit automatically starts a first watchdog time period until a first clear watchdog signal has been received; generating a first watchdog reset signal by a central processing unit of the microcontroller; and upon receipt of the first clear watchdog signal and following watchdog reset signals, the watchdog timer unit automatically starts a second watchdog time period which is different than the first watchdog time period. ### Claim 25 (depends on 24) The method according to claim 24, wherein a power-up of the microcontroller automatically activates the watchdog timer unit. ### Claim 26 (depends on 24) The method according to claim 24, wherein the first watchdog time period is endless. ### Claim 27 (depends on 24) The method according to claim 24, wherein the first watchdog time period is defined by a first timer and the second watchdog time period is defined by a second timer, the method comprising the step of switching the watchdog timer unit from the first timer to the second timer upon receipt of the first clear watchdog signal. ### Claim 28 (depends on 24) The method according to claim 24, wherein the first watchdog time period is defined by a first preset value stored in a first register and the second watchdog time period is defined by a second preset value stored in a second register, the method comprising the step of: upon activation of the watchdog timer unit, selecting the first register to preset a watchdog timer and upon receipt of a first clear watchdog signal, selecting the second register to preset the watchdog timer. ### Claim 29 (depends on 24) The method according to claim 24, wherein the first watchdog time period is defined by a first clock signal fed to the watchdog timer unit and the second watchdog time period is defined by a second clock signal fed to the watchdog timer unit, the method comprising the steps of: upon activation of the watchdog timer unit, selecting the first clock signal to clock a watchdog timer and upon receipt of a first clear watchdog signal, selecting the second clock signal to clock the watchdog timer. ### Claim 30 (depends on 24) The method according to claim 24, wherein upon activation of the watchdog timer unit a watchdog timer is preset directly with a first preset value and upon receipt of a first and any following clear watchdog signals, presetting the timer through a second preset value stored in a preset register. ### Claim 31 (depends on 24) The method according to claim 24, further comprising: upon receipt of a clear watchdog signal and a power fail signal the watchdog timer unit is configured to maintain a reset signal for predefined time period. ### Claim 32 (depends on 31) The method according to claim 31, wherein the predefined time period is defined by the second watchdog time period.