# US 2016/0253152 A1 · Splitable and scalable normalizer for vector data > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2016/0253152 A1 - Document ID: US20160253152A1 - Status: Published application - Kind: A1 - Application number: 15/151,062 - Filed: 2016-05-10 - Published: 2016-09-01 - Earliest claimed: 2013-09-03 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Maarten J. Boersma; Markus Kaltenbach; Christophe J. Layer; Silvia M. Mueller - Web page: https://patentgrep.com/patent/US20160253152A1 ## CPC - G06F 7/49936: {Normalisation mentioned as feature only} - G06F 7/00: Methods or arrangements for processing data by operating upon the order or content of the data handled (logic circuits H03K19/00) - G06F 7/483: Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} - G06F 7/49915: {Mantissa overflow or underflow in handling floating-point numbers} - G06F 9/30014: {with variable precision} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30189: {according to execution mode, e.g. mode flag} - G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]} - G06F 15/78: comprising a single central processing unit - G06F 15/8053: {Vector processors} - G06F 2207/382: Reconfigurable for different fixed word lengths - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A tool for supporting vector operations in a scalar data path. The tool determines a location for a split in the scalar mode configuration to enable vector mode operations. The tool determines the number of coarse shift multiplexers in conflict at a bit position receiving data from both the left half and the right half of the vector mode configuration. The tool duplicates a coarse shift multiplexer in conflict at the bit position receiving data from both the left half and the right half of the vector mode configuration. The tool duplicates an intermediate data signal in conflict at a signal position receiving data from both the left half and the right half of the vector mode configuration. The tool receives a control signal to split the scalar mode configuration and shift the leading zeros across the left half and the right half of the vector mode configuration. ## Claims ### Claim 1 A method for supporting vector operations in a scalar data path, the method comprising: determining a location for a split in the scalar mode configuration to enable vector mode operations, wherein the split occurs between the last coarse shift multiplexer of the left half, controlled by the left control signal, and the first coarse shift multiplexer of the right half, controlled by the right control signal; determining the number of coarse shift multiplexers in conflict at a bit position receiving data from both the left half and the right half of the vector mode configuration, wherein Rf−1 coarse shift multiplexers equals the number of coarse shift multiplexers in conflict, where Rf is defined as the number of data inputs of the fine shift multiplexers; duplicating a coarse shift multiplexer in conflict at the bit position receiving data from both the left half and the right half of the vector mode configuration, resulting in one or more coarse shift multiplexers sharing the bit position, wherein a left coarse shift multiplexer at the bit position receives the left control signal and a right coarse shift multiplexer at the bit position receives the right control signal; duplicating an intermediate data signal in conflict at a signal position receiving data from both the left half and the right half of the vector mode configuration, resulting in two intermediate data signals sharing the signal position, wherein a left intermediate data signal receives data from the left coarse shift multiplexer receiving the left control signal, and a right intermediate data signal receives data from the right coarse shift multiplexer receiving the right control signal; and receiving a control signal to split the scalar mode configuration and shift the leading zeros across the left half and the right half of the vector mode configuration, wherein the left half of the vector mode configuration receives the left control signal to independently control select signals left of the split, and the right half of the vector mode configuration receives the right control signal to independently control select signals right of the split. ### Claim 2 (depends on 1) The method of claim 1, wherein splitting the scalar mode configuration into the left half and the right half of the vector mode configuration, further comprising splitting the scalar mode configuration at the control level through independent control of select signals. ### Claim 3 (depends on 1) The method of claim 1, wherein determining the split location in the scalar mode configuration to enable vector mode operations, further comprises determining the split location through a formulaic relationship between the output string width, the number of fine shift multiplexers, the number of inputs per fine shift multiplexer, and the number of coarse shift multiplexers of the normalizer circuit; ### Claim 4 (depends on 3) The method of claim 3, wherein determining the split location through a formulaic relationship, further comprises determining the number coarse shift multiplexers assigned to the left half of the vector mode configuration, equal to “O+Rf−1,” and the number of coarse shift multiplexers assigned to the right half of the vector mode configuration, equal to “O+Rf−1,” where 0 is defined as the output width of the respective vector half. ### Claim 5 (depends on 1) The method of claim 1, wherein duplicating the coarse shift multiplexer in conflict at the bit position receiving data from both the left half and the right half of the vector mode configuration, further comprises duplicating fewer coarse shift multiplexers in conflict, equal to “Rf−1−D”, when open output bits, defined as “D” bits, exist between an output of the left half and an output of the right half in the vector mode configuration. ### Claim 6 (depends on 5) The method of claim 5, wherein duplicating fewer coarse shift multiplexers in conflict, further comprises determining the number of open output bits, wherein open output bits equal the total output string width of the singular scalar mode configuration minus the total output string width of both the left half and right half of the vector mode configuration. ### Claim 7 A computer program product for supporting vector operations in a scalar data path, the computer program product comprising: one or more computer readable storage media and program instructions stored on the one or more computer readable storage media, the program instructions comprising: program instructions to determine a location for a split in the scalar mode configuration to enable vector mode operations, wherein the split occurs between the last coarse shift multiplexer of the left half, controlled by the left control signal, and the first coarse shift multiplexer of the right half, controlled by the right control signal; program instructions to determine the number of coarse shift multiplexers in conflict at a bit position receiving data from both the left half and the right half of the vector mode configuration, wherein Rf−1 coarse shift multiplexers equals the number of coarse shift multiplexers in conflict, where Rf is defined as the number of data inputs of the fine shift multiplexers; program instructions to duplicate a coarse shift multiplexer in conflict at the bit position receiving data from both the left half and the right half of the vector mode configuration, resulting in one or more coarse shift multiplexers sharing the bit position, wherein a left coarse shift multiplexer at the bit position receives the left control signal and a right coarse shift multiplexer at the bit position receives the right control signal; program instructions to duplicate an intermediate data signal in conflict at a signal position receiving data from both the left half and the right half of the vector mode configuration, resulting in two intermediate data signals sharing the signal position, wherein a left intermediate data signal receives data from the left coarse shift multiplexer receiving the left control signal, and a right intermediate data signal receives data from the right coarse shift multiplexer receiving the right control signal; and program instructions to receive a control signal to split the scalar mode configuration and shift the leading zeros across the left half and the right half of the vector mode configuration, wherein the left half of the vector mode configuration receives the left control signal to independently control select signals left of the split, and the right half of the vector mode configuration receives the right control signal to independently control select signals right of the split. ### Claim 8 (depends on 7) The computer program product of claim 7, further comprise: program instructions to split the scalar mode configuration into the left half and the right half of the vector mode configuration, further comprising splitting the scalar mode configuration at the control level through independent control of select signals. ### Claim 9 (depends on 7) The computer program product of claim 7, wherein program instructions to determine the split location in the scalar mode configuration to enable vector mode operations, further comprises determining the split location through a formulaic relationship between the output string width, the number of fine shift multiplexers, the number of inputs per fine shift multiplexer, and the number of coarse shift multiplexers of the normalizer circuit; ### Claim 10 (depends on 9) The computer program product of claim 9, wherein determining the split location through a formulaic relationship, further comprise program instructions to determine the number coarse shift multiplexers assigned to the left half of the vector mode configuration, equal to “O+Rf−1,” and the number of coarse shift multiplexers assigned to the right half of the vector mode configuration, equal to “O+Rf−1,” where O is defined as the output width of the respective vector half. ### Claim 11 (depends on 7) The computer program product of claim 7, wherein program instructions to duplicate the coarse shift multiplexer in conflict at the bit position receiving data from both the left half and the right half of the vector mode configuration, further comprise program instructions to duplicate fewer coarse shift multiplexers in conflict, equal to “Rf−1−D”, when open output bits, defined as “D” bits, exist between an output of the left half and an output of the right half in the vector mode configuration. ### Claim 12 (depends on 11) The computer program product of claim 11, wherein program instructions to duplicate fewer coarse shift multiplexers in conflict, further comprise program instructions to determine the number of open output bits, wherein open output bits equal the total output string width of the singular scalar mode configuration minus the total output string width of both the left half and right half of the vector mode configuration. ### Claim 13 A computer system for supporting vector operations in a scalar data path, the computer system comprising: one or more computer processors; one or more computer readable storage media; program instructions stored on at least one of the one or more computer readable storage media for execution by at least one of the one or more computer processors, the program instructions comprising: program instructions to determine a location for a split in the scalar mode configuration to enable vector mode operations, wherein the split occurs between the last coarse shift multiplexer of the left half, controlled by the left control signal, and the first coarse shift multiplexer of the right half, controlled by the right control signal; program instructions to determine the number of coarse shift multiplexers in conflict at a bit position receiving data from both the left half and the right half of the vector mode configuration, wherein Rf−1 coarse shift multiplexers equals the number of coarse shift multiplexers in conflict, where Rf is defined as the number of data inputs of the fine shift multiplexers; program instructions to duplicate a coarse shift multiplexer in conflict at the bit position receiving data from both the left half and the right half of the vector mode configuration, resulting in one or more coarse shift multiplexers sharing the bit position, wherein a left coarse shift multiplexer at the bit position receives the left control signal and a right coarse shift multiplexer at the bit position receives the right control signal; program instructions to duplicate an intermediate data signal in conflict at a signal position receiving data from both the left half and the right half of the vector mode configuration, resulting in two intermediate data signals sharing the signal position, wherein a left intermediate data signal receives data from the left coarse shift multiplexer receiving the left control signal, and a right intermediate data signal receives data from the right coarse shift multiplexer receiving the right control signal; and program instructions to receive a control signal to split the scalar mode configuration and shift the leading zeros across the left half and the right half of the vector mode configuration, wherein the left half of the vector mode configuration receives the left control signal to independently control select signals left of the split, and the right half of the vector mode configuration receives the right control signal to independently control select signals right of the split. ### Claim 14 (depends on 13) The computer system of claim 13, further comprise: program instructions to split the scalar mode configuration into the left half and the right half of the vector mode configuration, further comprising splitting the scalar mode configuration at the control level through independent control of select signals. ### Claim 15 (depends on 13) The computer system of claim 13, wherein program instructions to determine the split location in the scalar mode configuration to enable vector mode operations, further comprises determining the split location through a formulaic relationship between the output string width, the number of fine shift multiplexers, the number of inputs per fine shift multiplexer, and the number of coarse shift multiplexers of the normalizer circuit; ### Claim 16 (depends on 15) The computer system of claim 15, wherein determining the split location through a formulaic relationship, further comprise program instructions to determine the number coarse shift multiplexers assigned to the left half of the vector mode configuration, equal to “O+Rf−1,” and the number of coarse shift multiplexers assigned to the right half of the vector mode configuration, equal to “O+Rf−1,” where 0 is defined as the output width of the respective vector half. ### Claim 17 (depends on 13) The computer system of claim 13, wherein program instructions to duplicate the coarse shift multiplexer in conflict at the bit position receiving data from both the left half and the right half of the vector mode configuration, further comprise program instructions to duplicate fewer coarse shift multiplexers in conflict, equal to “Rf−1−D”, when open output bits, defined as “D” bits, exist between an output of the left half and an output of the right half in the vector mode configuration. ### Claim 18 (depends on 17) The computer system of claim 17, wherein program instructions to duplicate fewer coarse shift multiplexers in conflict, further comprise program instructions to determine the number of open output bits, wherein open output bits equal the total output string width of the singular scalar mode configuration minus the total output string width of both the left half and right half of the vector mode configuration.