Vertical transistor and local interconnect structure

A semiconductor structure comprising:

• a gate electrode laterally contacted by a pair of gate dielectrics;
• a pair of semiconductor channels contacting a respective gate dielectric among the pair of gate dielectrics;
• a pair of top doped semiconductor regions adjoined to a respective top portion of the pair of semiconductor channels;
• a bottom doped semiconductor region contacting lower portions of outer sidewalls of the pair of gate dielectrics, and adjoined to bottom portions of the pair of semiconductor channels;
• and
• a metallic material layer contacting a bottom surface of the bottom doped semiconductor region and located on, or within, a substrate,
• wherein:
• outer sidewalls of the pair of semiconductor channels, outer sidewalls of the pair of top doped semiconductor regions, and outer sidewalls of the bottom doped semiconductor region are located within a pair of vertical planes;
• and
• the outer sidewalls of the bottom doped semiconductor region are adjoined to a top surface of the metallic material layer.

A semiconductor structure comprising:

• a gate electrode laterally contacted by a pair of gate dielectrics;
• a pair of semiconductor channels contacting a respective gate dielectric among the pair of gate dielectrics;
• a bottom doped semiconductor region having a doping of a first conductivity type, contacting lower portions of outer sidewalls of the pair of gate dielectrics, and adjoined to bottom portions of the pair of semiconductor channels;
• and
• a pair of top doped semiconductor regions adjoined to a respective top portion of the pair of semiconductor channels and having a doping of a second conductivity type that is the opposite of the first conductivity type.

A method of forming a semiconductor device, comprising:

• forming a layer stack comprising, from bottom to top, a bottom semiconductor layer, a bottom dielectric spacer layer, a conductive material layer, and a top dielectric spacer layer over a substrate;
• forming a first patterned stack and a second patterned stack by patterning the layer stack;
• forming first gate dielectrics on sidewalls of the first patterned stack, and second gate dielectrics on sidewalls of the second patterned stack;
• forming first vertical semiconductor portions on the first gate dielectrics and second vertical semiconductor portions on the second gate dielectrics;
• removing the second vertical semiconductor portions while masking the first vertical semiconductor portions;
• and
• forming a vertical switching device by introducing electrical dopants to top regions of the first vertical semiconductor portions and to bottom regions of the first vertical semiconductor portions, wherein a portion of the conductive material layer within the first patterned stack is a gate electrode that controls a state of the vertical switching device.