Middle-of-line integration methods and semiconductor devices
AssigneeQUALCOMM Incorporated
InventorsJohn Jianhong Zhu, Da Yang, Jeffrey Junhao Xu, Stanley Seungchul Song, Kern Rim
Life of this patent
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Abstract
An electronic device includes a middle-of-line (MOL) stack. The electronic device includes a top local interconnect layer and a contact coupling the top local interconnect layer to a gate of a semiconductor device through a first dielectric layer. The electronic device also includes one or more isolation walls between the contact and the first dielectric layer, wherein the one or more isolation walls include aluminum nitride (AlN).
Claims21
An electronic device comprising:
- a top local interconnect layer of a middle-of-line (MOL) stack;
- a contact coupling the top local interconnect layer to a gate of a semiconductor device through a first dielectric layer;
- and
- one or more isolation walls between the contact and the first dielectric layer, wherein the one or more isolation walls include aluminum nitride (AlN).
A middle-of-line (MOL) integration method, comprising:
- etching a first dielectric layer and a second dielectric layer to form a first trench, the first dielectric layer positioned between the second dielectric layer and a gate of a semiconductor device;
- depositing a dielectric material into the first trench;
- and
- etching the dielectric material to form one or more isolation walls.
A non-transitory computer-readable medium comprising processor-executable instructions that, when executed by a processor, cause the processor to:
- initiate fabrication of an electronic device, the electronic device fabricated by:
- etching a first dielectric layer and a second dielectric layer to form a first trench, the first dielectric layer positioned between the second dielectric layer and a gate of a semiconductor device;
- depositing a dielectric material into the first trench;
- and
- etching the dielectric material to form one or more isolation walls.
An electronic device comprising:
- means for conducting;
- means for electrically coupling the means for conducting to a gate of a semiconductor device through a first dielectric layer;
- and
- means for isolating located between the means for electrically coupling and the first dielectric layer, wherein the means for isolating includes aluminum nitride (AlN).
Dependencies are inferred from the claim text.