US 2016/0240477 A1 · SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

Abstract

A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes an interconnect which includes an interconnect metal plug surrounded by a second metal layer. The interconnect is adjacent a sidewall of a dielectric, such that an air gap is between the interconnect and the sidewall of the dielectric. A protective barrier is over the interconnect and the air gap, and is over and in direct physical contact with a top surface of the dielectric. The interconnect metal plug surrounded by the second metal layer is less susceptible to damage than an interconnect metal plug that is not surrounded by a second metal layer. The protective barrier in direct physical contact with the dielectric reduces parasitic capacitance, which reduces an RC delay of the semiconductor arrangement, as compared to a semiconductor arrangement that does not have a protective barrier in direct physical contact with a dielectric.

Claims20

Dependent claims

A semiconductor arrangement, comprising:

a dielectric layer;
a first metal layer overlying a first portion of the dielectric layer, wherein:
a first void is defined by a first sidewall of the first metal layer and a first sidewall of the dielectric layer, and
the first sidewall of the first metal layer is spaced apart from the first sidewall of the dielectric layer by a first distance;
and
a first interconnect overlying the first metal layer and comprising:
a first interconnect metal plug;
and
a first interconnect metal layer surrounding sidewalls and a bottom surface of the first interconnect metal plug, wherein:
a second void is defined by a first sidewall of the first interconnect metal layer and a second sidewall of the dielectric layer, and
the first sidewall of the first interconnect metal layer is spaced apart from the second sidewall of the dielectric layer by a second distance different than the first distance.

8 more elements

Dependencies are inferred from the claim text.

Semiconductor arrangement and formation thereof

Life of this patent

Semiconductor arrangement and formation thereof

Life of this patent

Abstract

Claims20