Self-aligned integrated line and via structure for a three-dimensional semiconductor device

A monolithic three-dimensional NAND memory device comprising:

• a stack of alternating layers comprising electrically insulating layers and electrically conductive layers and located over a substrate;
• a memory opening extending through the stack;
• a memory film and a semiconductor channel located within the memory opening;
• at least one via level dielectric layer overlying the stack;
• at least one line level dielectric layer located above the at least one via level dielectric layer;
• and
• an integrated line and via structure comprising a first line structure and a via structure in contact with each other, wherein:
• the via structure comprises a conductive via liner contacting a sidewall of the at least one via level dielectric layer, a sidewall of the at least one line level dielectric layer, and a sidewall of the first line structure, and further comprises a conductive via fill material portion embedded within the conductive via liner,
• wherein:
• the integrated line and via structure further comprises a second line structure contacting the conductive via liner and additional sidewalls of the at least one line level dielectric layer;
• the via structure is embedded between edge sidewalls of the first and the second line structures to electrically connect the first and the second line structures together to form a bit line;
• bottom surfaces of the first and the second line structures are located above a bottom surface of the via structure;
• a bottom surface of the via structure physically contacts a drain region of a NAND string which comprises a part of the monolithic three-dimensional NAND memory structure;
• the bottom surfaces of the first and the second line structures do not physically contact the drain region of the NAND string;
• and
• the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device.

A method of manufacturing a metal interconnect structure, comprising:

• forming at least one via level dielectric layer over a substrate;
• forming at least one line level dielectric layer over the at least one via level dielectric layer;
• forming a line structure within the at least one line level dielectric layer;
• forming a mask layer including an opening over the at least one line level dielectric layer and the line structure, the opening in the mask layer overlying a portion of the line structure;
• forming a via cavity extending through the line structure and the at least one via level dielectric layer by etching a portion of the line structure underlying the opening and a portion of the at least one via level dielectric layer underlying the opening;
• and
• forming a via structure in the via cavity, wherein an integrated line and via structure comprising remaining portions of the line structure and the via structure is formed within a stack of the at least one via level dielectric layer and the at least one line level dielectric layer.