Semiconductor device, layout design and method for manufacturing a semiconductor device

An integrated circuit designing system, comprising:

• a non-transitory storage medium, the non-transitory storage medium configured to store a layout design of a semiconductor device and a set of instructions, the layout design comprising:
• a first interconnect structure layout pattern associated with forming a first interconnect structure of the semiconductor device, wherein the first interconnect structure layout pattern comprises:
• a first interconnect portion layout pattern associated with forming a first interconnect portion of the semiconductor device, wherein the first interconnect portion layout pattern has a width and a length;
• a second interconnect portion layout pattern associated with forming a second interconnect portion of the semiconductor device, wherein the second interconnect portion layout pattern has a width that is less than the length of the first interconnect portion layout pattern, and wherein the second interconnect portion layout pattern is connected to the first interconnect portion layout pattern;
• and
• a third interconnect portion layout pattern associated with forming a third interconnect portion of the semiconductor device, wherein the third interconnect portion layout pattern has a width less than the width of the second interconnect portion layout pattern, wherein the third interconnect portion layout pattern is connected to the second interconnect portion layout pattern;
• wherein the set of instructions is for generating an integrated circuit layout based on an original circuit design and the layout design of the semiconductor device;
• and
• a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute the set of instructions.

A semiconductor device comprising:

• a first interconnect portion having a first width and a first length;
• a second interconnect portion having a second width and a second length, wherein the second length is less than the first length, and the second interconnect portion is connected to the first interconnect portion;
• a third interconnect portion having a third width and a third length, wherein the third length is less than the second length, and the third interconnect portion is connected to the second interconnect portion;
• a fourth interconnect portion having a fourth width and a fourth length, wherein the fourth length is greater than the third length, and the fourth interconnect portion is connected to the third interconnect portion;
• and
• a fifth interconnect portion having a fifth width and a fifth length, wherein the fifth length is greater than the fourth length, and the fifth interconnection portion is connected to the fourth interconnect portion.