Semiconductor substrate, semiconductor package structure and method of making the same

A method of making a semiconductor package structure, comprising:

• providing a semiconductor substrate, the semiconductor substrate comprising:
• a first patterned metal layer;
• a second patterned metal layer spaced from and electrically connected to the first patterned metal layer;
• a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer and covering the second patterned metal layer, wherein the dielectric layer defines first openings exposing the second patterned metal layer;
• and
• a carrier layer abutting the dielectric layer;
• electrically connecting a die to the first patterned metal layer;
• and
• removing the carrier layer,
• wherein the dielectric layer has a surface roughness determined by a surface roughness of the carrier layer.

A method of making a semiconductor package structure, comprising:

• providing a semiconductor substrate, the semiconductor substrate comprising:
• a first patterned metal layer;
• a second patterned metal layer spaced from the first patterned metal layer;
• a first dielectric layer disposed between the first patterned metal layer and the second patterned metal layer;
• at least one via extending between and electrically connecting the first patterned metal layer and the second patterned metal layer;
• a second dielectric layer abutting the first dielectric layer and covering the second patterned metal layer, the second dielectric layer defining a plurality of first openings exposing the second patterned metal layer;
• and
• a carrier layer abutting the second dielectric layer and defining a plurality of second openings;
• electrically connecting a die to the first patterned metal layer;
• and
• removing the carrier layer,
• wherein the second dielectric layer has a surface roughness determined by a surface roughness of the carrier layer.

A semiconductor package structure, comprising:

• a semiconductor substrate, comprising:
• a first patterned metal layer;
• a second patterned metal layer, disposed adjacent to the first patterned metal layer;
• a dielectric layer, disposed between the first patterned metal layer and the second patterned metal layer and covering the second patterned metal layer, wherein the dielectric layer defines a plurality of first openings exposing the second patterned metal layer;
• at least one via extending from the first patterned metal layer to the second patterned metal layer, the at least one via electrically connecting the first patterned metal layer to the second patterned metal layer;
• and
• a die electrically connected to the first patterned metal layer.