Semiconductor Manufacturing Method and Tool
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYung-Yao Lee, Heng-Hsin Liu, Yi-Ping Hsieh, Ying Ying Wang
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Abstract
An overlay measurement and correction method and device is provided. In an embodiment the measurement device takes measurements of a first semiconductor wafer and uses the measurements in a plurality of correction techniques to generate an overlay correction model. The plurality of correction techniques include a first order correction, a first intra-field high order parameter correction and a first inter-field high order parameter correction. The model is used to adjust the exposure parameters for the exposure of the next semiconductor wafer. The process is repeated on each semiconductor wafer for a run-to-run analysis.
Claims20
A method of manufacturing a semiconductor device, the method comprising:
- exposing a first semiconductor wafer;
- performing a first series of measurements on the first semiconductor wafer to obtain a first set of overlay offset measurements;
- utilizing the first set of overlay offset measurements to generate a first overlay offset model based off of a first order correction, an intra-field higher order correction, and as inter-field higher order correction;
- generating a first set of overlay offsets from the first overlay offset model;
- exposing a second semiconductor wafer based at least in part on the first set of overlay offset, wherein the second semiconductor wafer is exposed directly after the exposing the first semiconductor wafer;
- performing a second series of measurements on the second semiconductor wafer to obtain a second set of overlay offset measurements;
- and
- utilizing the second set of overlay offset measurements to generate a second overlay offset model based off of the first order correction, the intra-field higher order correction, and the inter-field higher order correction.
A method of manufacturing a semiconductor device, the method comprising:
- taking a first set of overlay offset measurements of a first semiconductor wafer;
- performing a plurality of correction analyses on the first set of overlay offset measurements to generate a first overlay offset model, wherein the plurality of correction analyses further comprises:
- a first order correction;
- a first intra-field higher order correction;
- and
- a first inter-field higher order correction;
- utilizing the overlay offset model to expose a second semiconductor wafer, wherein the second semiconductor wafer is the next semiconductor wafer to be exposed after the first semiconductor wafer;
- taking a second set of overlay offset measurements of the second semiconductor wafer;
- and
- performing the plurality of correction analyses on the second set of overlay offset measurements to generate a second overlay offset model.
An overlay correction unit comprising:
- a measurement unit configured to perform run-to-run measurements on each of a plurality of semiconductor wafers;
- and
- a model generation unit, wherein the model generation unit is configured to generate a plurality of models using a series of correction techniques, each of the plurality of models being generated from a corresponding one of the plurality of semiconductor wafers, wherein the series of correction techniques comprises:
- a first order correction;
- a first intra-field higher order parameter correction;
- and
- a first inter-field higher order parameter correction.
Dependencies are inferred from the claim text.