Weak bit detection using on-die voltage modulation

A method, comprising:

• storing test data in first subset of a plurality of data storage cells included in a memory;
• changing, by a first regulation unit, a first voltage level supplied to a first power terminal coupled to each data storage cell of the first subset of the plurality of data storage cells from a first value to a second value, wherein the second value is different than the first value, wherein the first regulation circuit is included on the same die with the memory;
• generating, by a second regulation unit, a second voltage level supplied to a second power terminal coupled to each data storage cell of a second subset of the plurality of data storage cells;
• reading first data from the first subset of the plurality of data storage cells;
• changing the first voltage level from the second value to the first value;
• reading second data from the first subset of the plurality of data storage cells;
• and
• comparing the second data to the test data.

A system, comprising:

• a processor;
• and
• a memory coupled to the processor, wherein the memory includes a plurality of data storage cells, a first regulation circuit and a second regulation circuit, and wherein the memory is configured to:
• receive test data from the processor;
• store the test in a first subset of the plurality of data storage cells;
• wherein the first regulation circuit is configured to change a first voltage level supplied to a first power terminal coupled to each data storage cell included in the first subset of the plurality of data storage cells from a first value to a second value, wherein the second value is different than the first value;
• wherein the second regulation circuit is configured to generate a second voltage level supplied to a second power terminal coupled to each data storage cell included in a second subset of the plurality of data storage cells;
• wherein the memory is further configured to:
• read first data from the first subset of the plurality of data storage cells;
• change the first voltage level from the second value to the first value;
• read second data from first subset of the plurality of data storage cells;
• and
• compare the second data with the test data.