Systems, devices and methods for memory operations
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYUE-DER CHIH, CHENG-HSIUNG KUO, GU-HUAN LI, CHUNG-CHIEH CHEN
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Abstract
Systems, devices and methods are provided for memory operations. An example system includes: a latch circuit shared by a plurality of memory blocks of a memory device and configured to provide one or more regulation signals for a memory operation; a source line circuit shared by the plurality of memory blocks and configured to provide a source line voltage to the plurality of memory blocks for the memory operation based at least in part on the one or more regulation signals; and a plurality of driver circuits configured to provide a plurality of drive signals to the plurality of memory blocks based at least in part on the one or more regulation signals.
Claims20
A system for memory operations, the system comprising:
- a memory device including a plurality of memory blocks;
- a latch circuit shared by the plurality of memory blocks and configured to provide first and second regulation signals for a memory operation;
- a source line circuit shared by the plurality of memory blocks and configured to provide a source line voltage to the plurality of memory blocks for the memory operation based at least in part on the second regulation signal;
- and
- a plurality of driver circuits configured to provide a plurality of drive signals to the plurality of memory blocks based at least in part on the first regulation signal.
(canceled)
A memory device comprising:
- a plurality of memory blocks;
- a common source line shared by the plurality of memory blocks;
- and
- a sector driver circuit shared by the plurality of memory blocks, the sector driver circuit being configured to provide a source line voltage to the common source line and provide a plurality of drive signals to the plurality of memory blocks for a memory operation.
A method comprising:
- providing first and second regulation signals for a memory operation involving a plurality of memory blocks of a memory device;
- providing a common source line voltage to the plurality of memory blocks for the memory operation based at least in part on the first regulation signal;
- and
- providing a plurality of drive signals to the plurality of memory blocks based at least in part on the second regulation signal.
Dependencies are inferred from the claim text.