Screening for Later Life Stuck Bits in Ferroelectric Memories

A method of testing a plurality of integrated circuits formed in a single integrated circuit wafer, each of the plurality of integrated circuits including ferroelectric memory cells, the method comprising the steps of:

• baking the wafer at a first elevated temperature for a first selected duration;
• then heating the wafer to a second elevated temperature lower than the first elevated temperature;
• and
• then performing a multiprobe test on the wafer at the second elevated temperature, for each of the plurality of integrated circuits, the multiprobe test comprising:
• reading each of a plurality of the memory cells programmed to a first data state corresponding to a lower polarization capacitance, at each of a plurality of reference voltages, to determine a first reference voltage at which a first one of the plurality of memory cells fails to return the first data state when read, and a second reference voltage at which a selected number of the plurality of memory cells fails to return the first data state when read;
• and
• comparing a slope of a line in the failed bit count versus reference voltage plane indicated by the first and second reference voltages with a slope limit to determine whether one or more of the plurality of memory cells in the integrated circuit constitute stuck bits.