Resistive memory system and method of operating the resistive memory system

A resistive memory system comprising:

• a memory cell array including a plurality of resistive memory cells;
• and
• an encoder for generating write data to be programmed to a memory cell array to at least one of a plurality of states by encoding input data such that at least one of the number of memory cells to be programmed to a first state and the number of memory cells to be programmed to a second state is reduced,
• wherein a resistance level of the first state is second highest among resistance levels of the plurality of states, and a resistance level of the second state is third highest among the resistance levels of the plurality of states.

A memory controller comprising:

• a processor that determines whether data is to be encoded prior to being programmed into memory cells of a nonvolatile memory, wherein each of the memory cells is assigned one of a plurality of un-encoded information states, respectively corresponding to programmable resistance levels of the memory cells, for representing the data;
• and
• an encoder that encodes the data, for an affirmative determination by the processor, such that:
• one of a plurality of encoded information states, respectively corresponding to the programmable resistance levels, is assigned to each of the memory cells, and
• the number of memory cells to which a predetermined first encoded information state, among the encoded information states, has been assigned is always reduced with respect to the number of memory cells to which a predetermined Nth un-encoded information state, among the un-encoded information states, has been assigned.