Accessing memory cells in parallel in a cross-point array
AssigneeMicron Technology, Inc.
InventorHernan A. Castro
Life of this patent
Estimating the term…
Abstract
Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.
Claims21
(canceled)
A method of accessing memory cells in parallel, comprising:
- selecting a first memory cell in a first column and a first row of a cross-point memory array;
- selecting a second memory cell in a second column and a second row of the cross-point memory array;
- applying a first threshold bias to the first memory cell during a first threshold period;
- applying a second threshold bias to the second memory cell during a second threshold period that overlaps with the first threshold period;
- and
- accessing the first memory cell during the first threshold period and the second memory cell during the second threshold period.
A method of accessing memory cells in an array of memory cells, comprising:
- determining at least two memory cells in an array;
- selecting at least two columns in the array that each correspond to one of the at least two memory cells;
- selecting at least two rows in the array that each correspond to one of the at least two memory cells;
- and
- simultaneously accessing the at least two memory cells in the array based at least in part on applying a bias to the at least two memory cells in the array.
A memory device, comprising:
- a first memory cell and a second memory cell each including:
- a selector node positioned between a first electrode and a second electrode, wherein the first electrode contacts a column oriented in a first direction;
- a storage node positioned between the second electrode and a third electrode, wherein the third electrode contacts a row oriented in a second direction;
- and
- a memory controller to simultaneously access the first memory cell and the second memory cell based at least in part on applying a bias to the first memory cell and the second memory cell.
Dependencies are inferred from the claim text.