US 2016/0240246 A1 · SEMICONDUCTOR STORAGE DEVICE

Abstract

A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

Claims24

Dependent claims

1-8. (canceled)

A semiconductor device comprising:

a plurality of word lines;
a pair of bit lines;
a plurality of static type memory cells coupled to the plurality of word lines and the pair of bit lines so that one memory cell is coupled to one word line and the pair of bit lines, each memory cell being coupled between a first voltage and a second voltage lower than the first voltage;
a write driver circuit which transmits data to the pair of bit lines according to write data;
and
a write assist circuit which drives one of the pair of bit lines to a third voltage lower than the second voltage, the one of the pair of bit lines corresponding to a low potential side of the pair of bit lines according to the write data,
wherein the write assist circuit comprises:
a first signal wiring;
a first driver circuit which drives the first signal wiring according to a control signal;
and
a second signal wiring coupled to the bit line on the low potential side and operable to generate the third voltage by the driving of the first driver circuit, based on a coupling capacitance between the first signal wiring and the second signal wiring.

8 more elements

A semiconductor device comprising:

a plurality of word lines arranged along a first direction;
a pair of bit lines arranged along a second direction different from the first direction;
a plurality of static type memory cells coupled to the plurality of word lines and the pair of bit lines so that one memory cell is coupled to one word line and the pair of bit lines, each memory cell being coupled between a first voltage and a second voltage lower than the first voltage;
a first voltage signal wiring arranged along the second direction and operable to supply the first voltage;
and
a second voltage signal wiring arranged along the second direction and operable to supply the second voltage;
a write driver circuit which transmits data to the pair of bit lines according to write data;
and
a write assist circuit which drives one of the pair of bit lines to a third voltage lower than the second voltage, the one of the pair of bit lines corresponding to a low potential side of the pair of bit lines according to the write data,
the write assist circuit comprising:
a first signal wiring arranged along the second direction;
a first driver circuit which drives the first signal wiring according to a control signal;
and
a second signal wiring arranged along the second direction and coupled to the bit line on the low potential side and operable to generate the third voltage by the driving of the first driver circuit, based on a coupling capacitance between the first signal wiring and the second signal wiring,
wherein the first signal wiring, the second signal wiring, the first voltage signal wiring, and the second voltage signal wiring are arranged by the same metallic wiring layer.

12 more elements

A semiconductor device comprising:

a plurality of word lines arranged along a first direction;
a pair of bit lines arranged along a second direction different from the first direction;
a plurality of static type memory cells coupled to the plurality of word lines and the pair of bit lines so that one memory cell is coupled to one word line and the pair of bit lines, each memory cell being coupled between a first voltage and a second voltage lower than the first voltage;
a first voltage signal wiring arranged along the second direction and operable to supply the first voltage;
a second voltage signal wiring arranged along the second direction and operable to supply the second voltage;
a write driver circuit which transmits data to the pair of bit lines according to write data;
and
a write assist circuit which drives one of the pair of bit lines to a third voltage lower than the second voltage, the one of the pair of bit lines corresponding to a low potential side of the pair of bit lines according to the write data, the write assist circuit comprising:
a first signal wiring arranged along the second direction;
a first driver circuit which drives the first signal wiring according to a control signal;
and
a second signal wiring arranged along the second direction and coupled to the bit line on the low potential side and operable to generate the third voltage by the driving of the first driver circuit, based on a coupling capacitance between the first signal wiring and the second signal wiring,
wherein the first signal wiring and the second signal wiring are provided between the first voltage signal wiring and the second voltage signal wiring.

10 more elements

A semiconductor device comprising:

a plurality of word lines arranged along a first direction;
a pair of bit lines arranged along a second direction different from the first direction;
a plurality of static type memory cells coupled to the plurality of word lines and the pair of bit lines so that one memory cell is coupled to one word line and the pair of bit lines, each memory cell being coupled between a first voltage and a second voltage lower than the first voltage;
a first voltage signal wiring arranged along the second direction and operable to supply the first voltage;
a second voltage signal wiring operable to supply the second voltage;
a write driver circuit which transmits data to the pair of bit lines according to write data;
and
a write assist circuit which drives one of the pair of bit lines to a third voltage lower than the second voltage, the one of the pair of bit lines corresponding to a low potential side of the pair of bit lines according to the write data, the write assist circuit comprising:
a first signal wiring arranged along the second direction;
a first driver circuit which drives the first signal wiring according to a control signal;
and
a second signal wiring arranged along the second direction and coupled to the bit line on the low potential side and operable to generate the third voltage by the driving of the first driver circuit, based on a coupling capacitance between the first signal wiring and the second signal wiring,
wherein the first signal wiring, the second signal wiring, and the first voltage signal wiring are arranged by the same metallic wiring layer.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application

15/134,981Filed 21 Apr 2016

Priority

JP 2014-06181225 Mar 2014

Published

18 Aug 2016

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 11/419
For memory cells of the field-effect type: read-write [R-W] circuits
G11C 7/12
Arrangements for writing information into, or reading information out from, a digital store: bit line control circuits, e.g. drivers, boosters,…
G11C 11/418
For memory cells of the field-effect type: address circuits
G11C 8/16
Arrangements for selecting an address in a digital store: multiple access memory array, e.g. addressing one storage element via at least two…

Semiconductor storage device

Life of this patent

Semiconductor storage device

Life of this patent

Abstract

Claims24