US 2016/0240243 A1 · SEMICONDUCTOR DEVICE

Abstract

A semiconductor device capable of reconfiguration, including a plurality of logic units which are connected to each other by an address line or a data line, wherein each of the logic units includes: a plurality of address lines; a plurality of data lines; a clock signal line to receive a system clock signal; a first and a second memory cell units which operate synchronously with the clock signal; a first address decoder which decodes an address signal and outputs a decode signal to the first memory cell unit; a second address decoder which decodes an address signal and outputs a decode signal to the second memory cell unit; and an address transition detection unit which generates an internal clock signal and outputs the internal clock signal to the first memory cell unit, when a transition of the address signal input from the plurality of address lines is detected, wherein the first memory cell unit operates synchronously with the internal clock signal, and the second memory cell unit operates synchronously with the system clock signal.

Claims20

Dependent claims

A system on chip device characterized by comprising:

a processor which executes calculation processing synchronously with a clock;
a storage unit which operates asynchronously with the clock;
and
an address transition detection unit which detects a transition of an address output from the processor to the storage unit, wherein
the address transition detection unit activates a word line of the storage unit which operates asynchronously, when the address transition detection unit detects the transition of the address.

2 more elements

A semiconductor device capable of reconfiguration, characterized by comprising a plurality of logic units which are connected to each other by an address line or a data line, wherein

each of the logic units includes:
a plurality of address lines;
a plurality of data lines;
a clock signal line to receive a system clock signal;
a first and a second memory cell units which operate synchronously with the clock signal;
a first address decoder which decodes an address signal and outputs a decode signal to the first memory cell unit;
a second address decoder which decodes an address signal and outputs a decode signal to the second memory cell unit;
and
an address transition detection unit which generates an internal clock signal and outputs the internal clock signal to the first memory cell unit, when a transition of the address signal input from the plurality of address lines is detected, wherein
the first memory cell unit operates synchronously with the internal clock signal, and the second memory cell unit operates synchronously with the system clock signal.

7 more elements

A control method of a semiconductor device capable of reconfiguration, characterized by the semiconductor device capable of reconfiguration comprising a plurality of logic units which are connected to each other by an address line or a data line, wherein

each of the logic units includes:
a plurality of address lines;
a plurality of data lines;
a clock signal line to receive a system clock signal;
a first address decoder;
a second address decoder;
a first memory cell unit including a plurality of memory cells and operates synchronously with the clock signal;
a second memory cell unit including a plurality of memory cells and operates synchronously with the clock signal;
and
an address transition detection unit which generates an internal clock signal and outputs the internal clock signal to the first memory cell unit, when a transition of an address signal input from the plurality of address lines is detected, wherein
the first address decoder decodes the address signal, and outputs a decode signal to the first memory cell unit,
the first address decoder decodes the address signal, and outputs a decode signal to the second memory cell unit,
the first memory cell unit operates synchronously with the internal clock signal, and
the second memory cell unit operates synchronously with the system clock signal.

11 more elements

A storage medium which stores a program to control a semiconductor device capable of reconfiguration, characterized by the semiconductor device comprising a plurality of logic units which are connected to each other by an address line or a data line, wherein

each of the logic units includes:
a plurality of address lines;
a plurality of data lines;
a clock signal line to receive a system clock signal;
a first address decoder;
a second address decoder;
a first memory cell unit including a plurality of memory cells and operates synchronously with the clock signal;
a second memory cell unit including a plurality of memory cells and operates synchronously with the clock signal;
and
an address transition detection unit which generates an internal clock signal and outputs the internal clock signal to the first memory cell unit, when a transition of an address signal input from the plurality of address lines is detected, wherein
the first address decoder decodes the address signal, and outputs a decode signal to the first memory cell unit,
the first address decoder decodes the address signal, and outputs a decode signal to the second memory cell unit,
the first memory cell unit operates synchronously with the internal clock signal,
the second memory cell unit operates synchronously with the system clock signal,
the data line connected to the first memory cell unit and the data line connected to the second memory cell unit are connected to each other, and output a logical add, and
each of the first and the second memory cell units stores a program configuring truth value table data, and is configured as a logic element and/or a connection element, and wherein
the program makes the first or the second memory cell unit execute:
processing to operate as a logic circuit by outputting a logic calculation of a value stored in a memory cell specified by the address line connected by one side to a data line connected to an opposite of the one side;
and
processing to operate so that, when any one of the memory cell units is not used, the entire memory cell unit which is not used is made to output “0”.

17 more elements

Dependencies are inferred from the claim text.

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims20