Goa unit for co-driving gate and common electrodes, drive circuit and array

A GOA unit for co-driving a gate electrode and a common electrode, including:

• a trigger, having an input end, a clock end, a reset end, a low level input end and a trigger output end;
• a first selective input circuit, including two reverse cutoff diodes connected in parallel, wherein the anodes of the diodes are respectively connected with the outputs of the gate line n−1 and gate line n+2, and the cathodes of the diodes are used as outputs to be connected with the input end, in order to select level signals or edge signals in the gate line n−1 and gate line n+2 to serve as the input stimulus signal of the trigger;
• a second selective input circuit with an output thereof being connected with the clock end, including four clock pulse inputs having the same cycle but working asynchronously, a high level input for common electrode and a high level input for gate electrode, so as to respectively gate the high level input for common electrode and the high level input for gate electrode to the clock end of the trigger in different time sequences to pull up the voltage on the trigger output end;
• a third selective input circuit, including two reverse cutoff diodes connected in parallel, wherein the anodes of the diodes are respectively connected with the outputs of gate line n+1 and gate line n+4, and the cathodes of the diodes are used as outputs to be connected with the reset end, in order to select level signals or edge signals on gate line n+1 and gate line n+4 to serve as the reset signal of the trigger;
• a fourth selective input circuit with an output thereof being connected to the low level input end, for respectively gating a gate low level input or a common electrode low level input to the low level input end of the trigger under the control of signals on gate line n+1 and gate line n+4 to pull down the voltage thereon;
• and
• a selective output circuit with an input thereof being connected to the trigger output end, for selectively outputting a gate electrode driving signal or a common electrode driving signal in two of the four clock pulse sequences having the same cycle and working asynchronously.