Integrated circuit stack verification method and system for performing the same

A method of verifying an integrated circuit stack, the method comprising:

• determining a location of a first dummy layer based on a location of a first contact pad of a plurality of contact pads in a connecting substrate;
• determining a location of a second dummy layer based on a location of a second contact pad of the plurality of contact pads in the connecting substrate;
• adding the first dummy layer to a first contact pad of a functional circuit;
• adding the second dummy layer to a second contact pad of the functional circuit;
• converting the location of the first dummy layer on the first contact pad of the functional circuit to the first contact pad of the plurality of contact pads in the connecting substrate;
• converting the location of the second dummy layer on the second contact pad of the functional circuit to the second contact pad of the plurality of contact pads in the connecting substrate;
• performing a layout versus schematic (LVS) check of the connecting substrate including the first dummy layer and the second dummy layer;
• adjusting the location of at least one of the first dummy layer or the second dummy layer in the functional circuit if the connecting substrate fails the LVS check;
• and
• repeating, if the location of at least one of the first dummy layer or the second dummy layer is adjusted, converting the first dummy layer on the first contact pad of the functional circuit to the first contact pad of the plurality of contact pads in the connecting substrate, converting the second dummy layer on the second contact pad of the functional circuit to the second contact pad of the plurality of contact pads in the connecting substrate, and performing the LVS check of the connecting substrate based on the adjusted location of the first dummy layer or the second dummy layer.

A system for verifying an integrated circuit stack, the system comprising:

• a non-transitory computer readable medium configured to store instructions;
• and
• a processor connected to the non-transitory computer readable medium, wherein the processor is configured to execute the stored instructions for:
• adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate;
• converting the dummy layer location to the connecting substrate;
• determining whether the dummy layer is aligned with the contact pad of the connecting substrate;
• performing a layout versus schematic (LVS) check of the connecting substrate including the dummy layer;
• adjusting the dummy layer location in the functional circuit if the dummy layer location is misaligned with the contact pad of the connecting substrate or the connecting substrate fails the LVS check;
• and
• repeating, if the dummy layer location is adjusted, converting the dummy layer location to the connecting substrate, determining whether the dummy layer location is aligned with the contact pad of the connecting substrate, and performing the LVS check of the connecting substrate based on the adjusted dummy layer location.